Home Featured Articles High Performance High Density Interconnects Using Liquid Crystal Polymer-Substrates, Circuits Driven by Mobile Applications

High Performance High Density Interconnects Using Liquid Crystal Polymer-Substrates, Circuits Driven by Mobile Applications

310
0

by James Rathburn – HSIO Technologies, LLC

HSIO Technologies, LLC was established to define and develop alternative manufacturing and design capabilities for the printed circuit and connector marketplace to enable next generation performance and density. Relationships with leading semiconductor suppliers lead to the conclusion that conventional print, etch, and via formation techniques were reaching limitations in density and performance.

Domestically, there are many suppliers producing 75 micron line and space printed circuits using conventional print, etch, and drilling techniques. At the 50 micron line and space geometry, the number of suppliers is reduced and at the 25 to 30 micron line and space range availability is reduced further. Those suppliers who can provide lines in those ranges are typically etching thin copper in the 9 micron range and while making physical circuit connections, there is limited impedance control. With HDI and Build-Up technology used in packaging substrate applications, routing density is greater with signal and power  parasitic effects of concern. In general, HSIO has developed a set of design rules and manufacturing principles that leverage conventional circuit fabrication, while providing a roadmap for density and signal integrity improvements. The use of thin sections of fusion bonded Liquid Crystal Polymer (LCP) material, which is widely used in the connector industry, allows for a very tight control of impedance profiles (1-3%) with geometries in the 20-25 micron range and larger as the initial production target for rigid, flexible and semi-rigid printed circuits and package substrates with 10-15 micron geometries defined. The process developed is a combination of additive and subtractive techniques resulting in very well defined fine line circuit patterns with high aspect ratio vertical sidewalls that are completely surrounded with a near hermetic common low dielectric constant without glass weave. Solid copper Full Metal Vias provide vertical interconnect for signal layers with conventional power and ground cores.

Fabrication Building Blocks

To achieve fine line low loss signal performance beyond 40 GHz, the principle of traditional print and etch fabrication has limitations. The HSIO technology has several basic building blocks, where very thin 3 micron electroless copper is used as a base for circuit pattern electrolytic build-up using a resist defined pattern plate technique that, as an example, results in circuit cross sections of  25 microns wide and 18-20 microns thick. Solid copper vias are grown as part of the process.

After treatment, differential etch process is used to remove unwanted base copper, leaving the circuit patterns intact with nearly vertical sidewalls.

A fusion bonding process is used to encapsulate the circuit patterns in a manner that provides dielectric separation, leveling of the circuit pattern where spaces between circuits are filled, as well as the bonding mechanism for the next circuit layer.

Electroless plating is used to coat the vertical sidewalls of ablated vias. Electrolytic plating is used to form copper pillar full metal connections by growing from base metal up to the next metal layer, furthering the impedance match, increasing metal content with improved thermal and current carrying capabilities. In some cases, circuit patterns and vias are plated in the same process step with continuous bond.

The relatively thin dielectric spacing of LCP compared to glass laminates enables fine via formation with extremely straight vertical sidewalls and solid vias with a near 1:1 aspect ratio for reliable hole fill and plating growth.

A final LCP fusion step is used to complete external circuit layers, with final metal layer exposure for component mounting used in place of conventional solder mask which is very lossy from a signal integrity standpoint. The final LCP surface acts as the solder mask, providing a high speed path through the circuit all the way to the device terminal.

Above (Figure 6) showing final LCP mask that is optically translucent where metal features are visible to enable optical registration for pad exposure, eliminating solder mask registration issues.

The electroless and electrolytic plating process steps can be applied to create metal defined features flush with the LCP surface or extended beyond the surface as a pillar terminal.

Basic Design Rules

In general, the LCP film to be used for build-up is available in sheets that are 1, 2, 3, and 4 mils thick. The fusion bonding LCP films are available in thickness of 1.5, 2 and 3 mil thick. The variable stack-up to achieve impedance targets is made up of combining the various films as needed to achieve the proper dielectric separation and fusion bonding of layers. Solid copper layer to layer vias in the 1-3 mil range.

The basic design principle is to start with the appropriate LCP film with 3 micron or less copper. The circuit image is patterned into resist 1 mil thick as an example. The circuit pattern is plated to the top of the resist, resulting in circuits that are 28 microns thick. The resist is stripped and the pattern differential etched, resulting in a theoretical thickness of between 28 and 25 microns. The appropriate LCP fusion bonding film is used with a net dielectric thickness roughly 70-80% of pre-bonding thickness.

The drawing below illustrate basic design rules for a single ended and differential pair stripline design with appropriate dielectric and copper thickness as examples. There are many rules to define based upon circuit principles, refined lamination thickness and pattern plated copper thickness.

The adoption method is to consider an existing design that has conventional 3-5 mil line and space design rules, and apply the appropriate LCP design rules for the target design with the expected performance improved by 30-50% simply as a result of the LCP construction. Once design rules are adopted, finer line and space geometries are employed which can increase routing density and reduce layer count.

General Technology Benefits

An advantage of the LCP process is by pattern plating a crisp resist defined circuit field and controlled differential etch, final features can be created thicker with much better definition than traditional print and etch.  Traces are suspended in a common low dielectric material with very tight control of trace width and thickness as well as dielectric spacing not possible with existing methods.

Pattern Definition and Impedance Control

A significant benefit of the approach is the ability to achieve crisp pattern definition and conductor thickness. As a general rule, measurements suggest a parallel of approximately 1 ohm impedance impact for every 1 micron variance in conductor width and thickness. A comparison build was produced to evaluate the capability of conventional print and etch vs. the pattern plate fusion bond LCP process. The photos above (Figure 11) illustrate a high speed 28 Gbit package substrate with future needs 56 Gbit performance. The pattern plate process produces very crisp geometry with metal layers 18-20 microns thick.

The same circuitry shown in Figure 12 was created using the best available domestic print and etch capability from multiple suppliers. Significant erosion is present with reduction in trace integrity with metal layer 9 microns thick.

Another comparison study was conducted to compare conventional motherboard and backplane construction against the LCP fabrication process with an equivalent circuit. The LCP version of the circuit is 18x thinner with 60% improvement in system performance and insertion loss beyond 40 GHz.

Embedded Circuitry 

Additional benefits beyond fine line high aspect ratio traces are possible with the developed process. Geometries are not limited to simple round vias, and the additive nature of the process lends itself to creating vertical planar structures as an alternative to traditional stitched vias. An example includes the ability to create embedded coaxial or twin axial signal lines as a natural consequence of the pattern plating process.

As performance levels increase, there is significant desire to embedd passive function and decoupling directly in a printed circuit assembly or package substrate. The sequential process enables the option to place passive compoents within the assembly at the desired locations.

Cavities are created within the next level of LCP (Figure 15 & 16) such that upon fusion bonding the passive compoents are encapsulated with LCP and essentially near hermetically sealed within the circuit assembly.

Due to the ability to control metal layer thickness and dielectric separation much more closely than conventional construction (Figure 17), passive function can be printed as an alternative or supplement to discrete components.

Formable LCP

The unique nature of constructing a circuit stack with LCP enables the ability to create a 2 D metal structure suspended in surrounding LCP such as an RF shield.

The metalized structure can then be formed and fusion bonded to create a 3 D structure (Figure 18) to be SMT mounted into the system level assembly.

Components, embedded antennae and silicon can be incorporated on multiple surfaces in X, Y, and Z axis (Figure 19 & 20).

The LCP circuit structure can also be formed and fusion bonded to the enclosure or housing of an electronic device (Figure 21).

Conclusion

In conclusion, HSIO Technologies has worked with multiple leading semiconductor suppliers to develop and establish production processes for an evolutionary circuit fabrication process that leverages the properties of Liquid Crystal Polymer. Using the low dielectric constant LCP in thin fusion bondable layers, high aspect ratio fine line and space circuits are created with a mixture of additive and subtractive processes to create a tunable impedance environment much improved over the conventional 10% tolerance of conventional printed circuit construction. Solid copper full metal vias are grown in a layer by layer process supplemented with rigid cores and drilled plated through holes as needed for component attachment to the final assembly. Lossy conventional solder mask is eliminated with the final LCP bond layer acting as mask while offering the ability to extend terminals beyond the final mask layer if desired in a copper pillar configuration. The pattern plating process with very tight control of metal thickness and dielectric spacing allows for direct printing of passive function or the near hermetic encapsulation of discrete components. The fusion bondable nature of the LCP material also allows for embedded circuitry as well as creates a formable platform for creating 3 dimensional structures not possible with conventional circuit technology.

Acknowledgment

The author would like to acknowledge the various members of the HSIO Technologies staff and customer engineering groups who contributed to the definition of platforms, process development and validation testing.

Figure 1: Resist defined pattern plate enables finer line and space, very well defined geometries, tuned circuit thickness, and solid copper full metal vias
Figure 1: Resist defined pattern plate enables finer line and space, very well defined geometries, tuned circuit thickness, and solid copper full metal vias
Figure 2: Differential etch field metal enables finer line and space, tuned circuit thickness, near vertical side walls, and very little etch erosion
Figure 2: Differential etch field metal enables finer line and space, tuned circuit thickness, near vertical side walls, and very little etch erosion
Figure 3: Fusion bonded LCP characteristics are thin low dk sections, fusion bond thickness control, near hermetic, and common dk surrounds circuit
Figure 3: Fusion bonded LCP characteristics are thin low dk sections, fusion bond thickness control, near hermetic, and common dk surrounds circuit
Figure 4a: Near 1:1 aspect ratio for reliable hole fill and plating growth
Figure 4a: Near 1:1 aspect ratio for reliable hole fill and plating growth
Figure 4b: Near 1:1 aspect ratio for reliable hole fill and plating growth
Figure 4b: Near 1:1 aspect ratio for reliable hole fill and plating growth
Figure 5: Circuit layers
Figure 5: Circuit layers
Figure 6: Final LCP masks
Figure 6: Final LCP masks
Figure 7: Metal defined features
Figure 7: Metal defined features

Fig-08-Web

Figure 9: Fusion bonding LPC result in common dielectric all around the traces that tightly controlled. Trace shown 63.8 um wide by 24.9 um thick.
Figure 9: Fusion bonding LPC result in common dielectric all around the traces that tightly controlled. Trace shown 63.8 um wide by 24.9 um thick.
Figure 10a: Showing 2 mil via plated shut (10a) and showing added bumped - build up pads (10b)
Figure 10a: Showing 2 mil via plated shut (10a) and showing added bumped – build up pads (10b)
Figure 10b: Showing 2 mil via plated shut (10a) and showing added bumped - build up pads (10b)
Figure 10b: Showing 2 mil via plated shut (10a) and showing added bumped – build up pads (10b)
Figure 11a: LCP and pattern plated line with crisp controlled edges
Figure 11a: LCP and pattern plated line with crisp controlled edges
Figure 11b: LCP and pattern plated line with crisp controlled edges
Figure 11b: LCP and pattern plated line with crisp controlled edges
Figure 12a: Conventional print and etch – no uniform traces and side walls
Figure 12a: Conventional print and etch – no uniform traces and side walls
Figure 12b: Conventional print and etch – no uniform traces and side walls
Figure 12b: Conventional print and etch – no uniform traces and side walls
Figure 13: Comparison of circuit thickness
Figure 13: Comparison of circuit thickness
Figure 14a: Embedded Co-Ax (14a) & Twin Axial (14b)
Figure 14a: Embedded Co-Ax (14a) & Twin Axial (14b)
Figure 14b: Embedded Co-Ax (14a) & Twin Axial (14b)
Figure 14b: Embedded Co-Ax (14a) & Twin Axial (14b)
Figure 15: Figures 15 through 21are Examples of LCP usage
Figure 15: Figures 15 through 21are Examples of LCP usage
Figure 16: Figures 15 through 21are Examples of LCP usage
Figure 16: Figures 15 through 21are Examples of LCP usage
Figure 17a: Figures 15 through 21are Examples of LCP usage
Figure 17a: Figures 15 through 21are Examples of LCP usage
Figure 17b: Figures 15 through 21are Examples of LCP usage
Figure 17b: Figures 15 through 21are Examples of LCP usage
Figure 18: Figures 15 through 21are Examples of LCP usage
Figure 18: Figures 15 through 21are Examples of LCP usage
Figure 19: Figures 15 through 21are Examples of LCP usage
Figure 19: Figures 15 through 21are Examples of LCP usage
Figure 20: Figures 15 through 21are Examples of LCP usage
Figure 20: Figures 15 through 21are Examples of LCP usage
Figure 21: Figures 15 through 21are Examples of LCP usage
Figure 21: Figures 15 through 21are Examples of LCP usage

(310)

print

LEAVE YOUR COMMENT