by Peter Delos – Analog Devices
The heterodyne receiver has been the standard receiver option of choice for decades. In recent years, the rapid advance of analog to digital (A/D) converter sampling rates, the inclusion of embedded digital processing, and the integration of matched channels now offers options for the receiver architect that were not practical only a few years ago.
This article compares the benefits and challenges of three common receiver architectures, a heterodyne receiver, a direct sampling receiver, and a direct conversion receiver. Additional consideration on spurious, system noise, and dynamic range is also discussed. The intention is not to promote one option over others, but rather describe the pros and cons of the options and encourage the designer to select through engineering discipline the architecture most appropriate for the application.
Table 1 compares the heterodyne, direct-sampling, and direct-conversion architectures. The basic topology is shown along with some of the benefits and challenges of each architecture.
The heterodyne approach, is well proven and provides exceptional performance. The implementation is to mix to an intermediate frequency (IF). The IF frequency is chosen at a high enough frequency to allow practical filters in the operating band to provide good image rejection and LO isolation. It is also common to add an additional mixing stage to lower the frequency where very high dynamic range A/Ds are available. An additional feature is the receiver gain is distributed at different frequencies, thus risk of oscillation in high gain receivers is minimized. Through proper frequency planning the heterodyne receiver can be made with very good spurious and noise performance. Unfortunately, this architecture is the most complicated. It typically requires the most power and the largest physical footprint relative to the available bandwidth. In addition, frequency planning can be quite challenging at large fractional bandwidths. These challenges are significant with the modern quest towards low size, weight, and power (SWAP) combined with the desire for wide bandwidth and leads to designers considering of other architecture options when possible.
The direct sampling approach has long been sought after. The obstacles have been operating the converters at speeds commensurate with direct RF-sampling and achieving large input bandwidth. This architecture all the receiver gain is at the operating band frequency, so careful layout is required if large receiver gain is desired. Today, converters are available for direct sampling in higher Nyquist bands at both L- and S-Band. Advances are continuing: C-Band sampling will soon be practical, with X-Band sampling to follow.
Direct conversion architectures provide the most efficient use of the data converter bandwidth. The data converters operate in the first Nyquist where performance is optimum and low pass filtering is easier. The two data converters work together sampling I/Q signals, thus increasing the user bandwidth without the challenges of interleaving. The dominant challenge that has plagued the direct conversion architecture for years has been to maintain I/Q balance for acceptable levels of image rejection, LO leakage and DC offsets. In recent years the advanced integration of the entire direct conversion signal chain, combined with digital calibrations, has overcome these challenges and the direct conversion architecture is well positioned to be a very practical approach in many systems.
Frequency Plan Perspective
Figure 1 illustrates block diagrams and frequency plan examples of the three architectures. Figure 1a is an example of a heterodyne receiver with a high side LO mixing the operating band to the 2nd Nyquist zone of the A/D converter. The signal is further aliased to the 1st Nyquist for processing. Figure 1b shows a direct sampling receiver example. The operating band is sampled in the 3rd Nyquist zone, aliases to the 1st Nyquist, then an NCO is placed in the center of the band digitally down-converting to baseband, followed by filtering and decimation reducing the data rate commensurate with the channel bandwidth. Figure 1c is a direct conversion architecture example. By mating the dual A/D with a quadrature demodulator channel 1 samples the I (in phase) signal and channel 2 samples the Q (quadrature) signal.
Many modern A/D converters support all three architectures. For example, the AD9680 is a dual 1.25 GSPS A/D with programmable digital down-conversion. A dual A/D of this type supports two channel heterodyne and direct sampling architectures, or the converters can work as a pair in a direct conversion architecture.
The image rejection challenges of the direct conversion architecture can be quite difficult to overcome in a discrete implementation. With further integration combined with digitally assisted processing, the I/Q channels can be well matched leading to much improved image rejection. The receiver section of the recently released AD9371 is a direct conversion receiver and shown in Figure 2; note the similarity to Figure 1c.
Any design with frequency translation requires much effort to minimize unwanted frequencies folding in-band. This is the art of frequency planning and involves a balance of available components and practical filter design. Some of the spur folding concerns are briefly discussed and the designer is referred to the references for further explanation.
Figure 3 shows the folding of the A/D input frequency and the first two harmonics as a function of input frequency relative to the Nyquist band frequencies. For channel bandwidths much less than the Nyquist bandwidth, a goal for the receiver designer is to select operating points that place the folded harmonics out of the channel bandwidth.
The receiver downconversion mixer has additional complications. Any mixer creates harmonics inside the device. These harmonics all mix together and create additional frequencies. This effect is illustrated in Figure 4.
Figure 3 and Figure 4 only plot spurs up to the third order. In practice these are spurs of additional higher order are considered which quickly creates a spur free dynamic range issue for the designer. For narrow fractional bandwidths, meticulous frequency planning can overcome the mixer spurious problems. As bandwidths increase, the mixer spurious problem becomes a dominant obstacle. As A/D sampling frequencies increase, it is sometimes more practical for a direct sampling architecture to have lower spurious performance.
Much receiver design effort is placed on minimizing noise figure (NF). Noise figure is a measure of the degradation in signal to noise ratio.
The impact of a component or subsystem noise figure is that the output noise power is increased above the level of thermal noise and gain by the noise figure.
Noise Power Out = -174dBm/Hz + Gain(dB) + NF(dB)
Cascaded Noise Figure is calculated as:
The selection of receiver gain prior to the A/D and determining the required A/D SNR is a balance of the overall receiver noise figure and instantaneous dynamic range. Figure 5 provides a representation of the parameters to be considered. For illustrative purposes, the receiver noise is shown to be shaped by the anti-aliasing filter prior to the A/D, the A/D noise is shown as flat white noise, and the signal of interest is shown as a CW tone at -1 dBFs.
First, common units of either dBm or dBFs is needed. Converting the A/D noise from dBFs to dBm is known from the converter full scale level and the converter noise density.
The total noise is calculated as
This leads to the concept of A/D sensitivity loss. A/D sensitivity loss is a measure of the receiver noise degradation due to the A/D. To minimize this degradation, the receiver noise is desired to be well above the A/D noise. The limitation comes in the form of dynamic range and larger receiver gain limits the maximum signal received without A/D saturation. Thus the receiver designer faces a constant challenge of balancing dynamic range vs. noise figure.
The heterodyne, direct sampling, and direct conversion receiver architectures have been reviewed with emphasis on benefits and challenges of each architecture. Recent trends and considerations in receiver design have also been presented. With the world wide desire for more bandwidth, combined with the advancement of GSPS data converters, it is anticipated that many varied receiver designs will proliferate well into the future.
1. McClaning, Vito, “Radio Receiver Design,” New York, Noble Publishing, 2000.
2. “Fundamentals of RF and Microwave Noise Figure Measurements,” Keysight Application Note
3. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE, 1997
4. Delos, “Receiver Design Considerations In Digital Beamforming Phased Arrays,” Microwaves and RF, 2014
5. Henderson, “Mixers in Microwave Systems” WJ Tech-Note, 1990.
6. Harris, “What’s up with Digital Downconverters” Part 1 and 2, Analog Dialogue, 2016
7. Kester, “Analog-Digital Conversion,” Analog Devices, 2004
About the Author
Peter Delos is a Technical Lead at Analog Devices, Inc., in the Aerospace and Defense Group. He received his BSEE from Virginia Tech in 1990 and MSEE from NJIT in 2004.
He worked in the Naval Nuclear Power program from 1990 to 1997. This work included completion of the Naval Nuclear Power School Officer’s Program, work as an instructor in a Naval Submarine facility, and Lead Electrical Field Engineer work on the Seawolf class Submarines in Groton, CT.
In 1997, Peter accepted a position with Lockheed Martin in Moorestown NJ and began a prolific career developing receivers/exciters and synthesizers for multiple Radar and EW programs. This experience encompassed architecture definition, detailed design, rapid prototypes, manufacturing coverage, field installations, and coordination among many engineering disciplines. This work led the migration of phased array receiver/exciter electronics from centralized architectures to on-array digital beamforming systems.
In 2016, Peter accepted a position with Analog Devices in Greensboro, NC. He has nearly 20 years of experience in RF systems designing at the architecture level, PWB level, and IC level.