Home Featured Articles Design of a Broadband L-band 160W GaN Power Amplifier Using SMT Packaged Transistors 

Design of a Broadband L-band 160W GaN Power Amplifier Using SMT Packaged Transistors 


by  Plextek RFI & Qorvo

The design of a broadband power amplifier for L-band radar and wideband communications applications is described. Using a state-of-the-art Qorvo transistor in a cost-effective SMT plastic package, the amplifier has 160W output power between 1.2GHz and 1.8GHz and a typical efficiency of 55% for the complete connectorized PA. Particular consideration is given to the thermal challenges involved in using high-power GaN transistors in SMT packages. Two approaches to optimizing the thermal performance of the PCB have been compared; the first using an array of copper-filled vias beneath the ground paddle of the transistor, and the second using a copper coin embedded into the PCB.

Continuing advances in GaN technology are leading to operation at higher powers, supply voltages and frequencies. The QPD1013 transistor from Qorvo, shown in  Figure 1, utilizes 0.50µm GaN-on-SiC technology. It is packaged in a cost-effective 6.6 x 7.2 mm DFN (Dual Flat No Leads) package that allows for simpler PCB assembly compared to traditional metal-ceramic packages.

Qorvo’s GaN transistors are very efficient, but the high RF power levels under consideration mean that even an efficient PA will have significant power dissipation in the transistor. As the transistor is an SMT component, careful design of the PCB is required in order to optimize the thermal performance. Two approaches have been evaluated and the results of both are reported. The first makes use of an array of copper-filled vias beneath the ground paddle of the transistor and the second uses copper coin technology. A copper coin is a solid piece of copper (often known as a slug) embedded into the PCB during fabrication to allow efficient heat transfer from the transistor to the carrier on which the PCB is mounted. Many PCB manufacturers have experience with copper-filled via technology, but copper-coin techniques at RF frequencies are less well established.

Maximum Available Gain (MAG) was measured against frequency for three different sample transistors assembled on Rogers RO4350 with a thickness of 0.020”, at a transistor quiescent bias of 65V, 240mA.

Very good unit-to-unit consistency was demonstrated up to 6GHz. While the QPD1013 exhibits gain above 6GHz, for practical considerations its use is best suited to operation up to around 3.5GHz.

Load-pull measurements show that the transistor delivers over 52dBm (160W) of RF output power at efficiencies of around 70% when operated at 10% duty cycle and 100µs pulse width. This load-pull data was used as the basis for the large signal design of the PA.

Power Amplifier Design

The starting point for the PA design was to make the transistor unconditionally stable across the operating band. In-band stability must be ensured at the outset, and this was achieved by including an RC stability network at the RF input. The power dissipated in the series resistors is too high for conventional SMT components and so high-power aluminum nitride resistors from IMS were used. The amplifier is required to be unconditionally stable at all frequencies down to temperatures of -40°C, to allow the amplifier to operate across a broad range of temperatures. Low-frequency stability can be greatly improved with the addition of appropriate RC de-coupling at the bias feed points, which can be added later in the design process.

Initial load-pull data, provided by Qorvo, was used to determine the optimal load impedances for output power and drain efficiency between 1.2GHz and 1.8GHz. The QPD1013 delivers up to 200W under certain load conditions, but the operating efficiency also needed to be carefully considered to ensure the operating temperature of the transistor was acceptable. The load impedances that result in highest drain efficiency were selected as the target impedances to be presented by the output matching network. The corresponding RF output power level remained high, and the higher efficiency ensured acceptable thermal performance.

The output matching network utilized a bandpass topology to meet the target load impedances. The high operating voltages and high RF power levels present potential pitfalls to the unwary designer. It is vital to keep the RF tracks wide enough to avoid excessive temperature rise and potential destruction due to the very high RF power levels. Matching capacitors must be selected carefully to have adequate breakdown voltage to withstand the DC plus RF voltage swings with adequate Q to avoid excess power dissipation and reduced efficiency.

Planar EM simulations were performed on the metalwork of the output matching network, using Keysight Momentum, and the multi-port S-parameter block was simulated in conjunction with embedded high-frequency models of the 0805 SMT components. Figure 2 shows the hybrid EM/schematic of the output matching network circuit.

The simulated load impedance is plotted against the target on a Smith Chart normalized to 10Ω in Figure 3. Overlaying the simulated load curve on the supplied load-pull contours (the dotted trace) suggests that the target power and efficiency values will be met.

The simulated insertion loss of the output network was between 0.2dB and 0.4dB across the operating frequency range. Output matching network loss results from transmission line losses in the PCB dielectric and from SMT component losses. Even a fraction of a dB loss at these output power levels will amount to several watts of dissipated power, significantly reducing overall PA efficiency.

The input matching network adopted a low-pass architecture. IMS aluminum nitride resistors were used in the gate stability network. These can dissipate several watts of power, which allows the PA to withstand the high input drive levels of 10 – 20W required to operate the PA at P-3dB compression. Figure 4 shows the input matching network, which was simulated in the same manner as the output matching network.

It can be seen that the layout of both the input and output matching networks included inductive loops and solder pads to allow tuning of the PA performance following fabrication. These were ultimately not required, and the only post fabrication modifications were small changes to capacitor values. The simulated small signal performance of the PA demonstrated wide bandwidth and flat gain versus frequency response.

Thermal Considerations

GaN is capable of higher power densities than either LDMOS or GaAs. A consequence of this is that dissipated power needs to be removed efficiently from the package, in order to keep the junction temperature adequately low and ensure a long transistor lifetime.

The main heat transfer mechanism from the package is through the die-attach paddle into the PCB. Careful design of the PCB is essential to ensure good heat transfer to ambient which maintains the transistor temperature at a suitably low level. Two practical approaches were evaluated in the work, one using an array of copper filled vias — shown in Figure 5(b) —  and one using a copper coin fitted into the PCB, shown Figure 5(a). In both cases the PCB is mounted on an aluminum carrier.

Realization and Measured Performance

A photograph of one of the fully-assembled power amplifiers is shown in Figure 6. The hole in the front of the aluminum carrier allows a thermocouple to be placed directly below the QPD1013 transistor.

PAs were fabricated using both copper-filled vias and copper coin technology. The measured RF performance was very similar in both cases. The version with the copper coin did, however, offer improved thermal performance, with the transistor operating 10°C cooler compared with the copper-filled via PCB. Unless otherwise stated, the results presented below are for the copper-filled via version of the PCB.

Small-signal Measurements

The small-signal S-parameters of five PAs were measured with transistor base temperature of 25°C, -40°C and 85°C and demonstrated both consistency and a good agreement between simulation and measurement, as well as having good gain flatness across the operating band. The PA performance over temperature  showed the measured S21 is ~1 dB higher at -40°C and ~0.5 dB lower at 85°C, relative to the measurements at 25°C.

A comparison of the small-signal performance of a PA using copper filled vias with that of a PA using the copper coin PCB technology (Figure 7) showed that the RF performance of each is very similar, and this was also observed in the large signal performance.

Large-signal Measurements

The power transfer characteristics were measured for multiple PAs over temperature at 10% duty cycle, 128µs pulse width. The unit-to-unit performance was very similar, and the performance obtained for the copper-filled via PCB versions was similar to that obtained for the PAs using copper coin technology. The typical performance of one PA is plotted at three temperatures in Figure 8, where it can be seen that a minimum of 100W is delivered at the high end of the band and 160W at the low end. The typical efficiency of the complete PA, including output matching network and connector losses, is 55%. While the efficiency of the PA is impressive, the dissipated power can still exceed 100W, highlighting the need for an effective thermal solution.

The two-tone intermodulation performance of the PAs was also measured — the output IP3 is around +60dBm for a total RF output power of 10W (40dBm).


A GaN PA designed and realized using a commercially available SMT transistor that covers the 1.2 – 1.8GHz band and delivers an RF output power of around 160W with an efficiency of around 55%. The key performance data for the amplifier versus frequency is tabulated in Table 1.

As with all power transistors, careful thermal design is key to reliable operation. Variants of the PA have been fabricated and evaluated using two different PCB approaches to ensure good thermal performance. The RF performance was very similar in both cases, but the use of the copper coin PCB led to a 10°C reduction in channel temperature compared with the use of an array of copper-filled vias.

Although the improved thermal impedance of the copper coin PCB is attractive, great care must be taken to ensure that the surface of the PCB remains planar and that good contact is made between the copper coin and the ground paddle of the DFN. Any air gaps or solder voids can mitigate the inherent advantages of the copper coin approach.

Figure 1: The plastic-packaged QPD1013 transistor from Qorvo
Figure 2: EM simulated output match
Figure 3: Target (dotted) to simulated (solid) load impedance, 10Ω chart
Figure 4: EM simulated input match
Figure 5: (a), left, copper coin, and (b), right, copper-filled vias
Figure 6: Photograph of the manufactured PA
Figure 7: Comparison of S-parameters on copper-filled via PCB to copper coin PCB
Figure 8: Measured RF out at P-3dB over temperature
Table 1: Summary of measured performance