Analog Office 2004 Analog and RFIC Design System
Provides New Technologies for Next Generation EDA
by Tom Quan, Vice President of Marketing, Applied Wave Research, Inc.

The wireless revolution has profoundly influenced every aspect of modern living and will certainly become even more integral in the future in both business and private life. The consumer electronics industry, possibly more than any other, has been profoundly affected by the explosive demand for ever more feature-rich, smaller, more mobile, and more efficient gadgets. The fiercely competitive environment of this market puts relentless pressure on designers of the circuits and systems within these electronics products to develop increasingly complex chips that fit in smaller packages and use less power.

Electronic design automation (EDA) tools are crucial for the efficient design, simulation, and validation of the circuits and systems that enable these products to operate, and are key to streamlined design cycles that deliver them to market ahead of the competitive curve. Applied Wave Research, Inc. (AWR®) recently introduced Analog OfficeT 2004 design suite, an EDA solution that provides unique technology that specifically addresses the complex issues inherent in the design of analog and radio-frequency (RF) integrated circuits (ICs) for wireless products.

EDA has evolved over the past 20 years as isolated activities for each phase of a design. Legacy systems have separated the electrical design/analysis from the physical implementation domains at both the IC and package/module and printed circuit board (PCB) levels. EDA vendors have developed closed methodologies and tool sets for different design phases, requiring manual hand-offs and multiple iteration loops that result in costly errors and delays. The complexity of today's new semiconductor process technologies, as well as module implementation technologies, however, renders traditional design methods inadequate in terms of accuracy, efficiency, and cost.

The high-frequency circuit impairments in today's complex analog and RFICs, such as compression, noise, distortion, and phase noise, as well as the physical parasitics like interconnect impedance and coupling, are forcing the need to obtain complete "RF closure" between the RFIC's system and circuit, electrical and physical, and design and test activities before commitment to costly IC implementation.

Figure 1: AWR's Analog Office 2004 design system provides an entirely new approach that achieves optimum RF closure through a unified data model and design environment encompassing all of the design domains.

AWR has developed from the ground up the first completely new EDA design system in over 10 years. Analog Office 2004 software is built on an advanced software architecture, the unique core technology of which is a modern object-oriented data model that is inherently open and flexible. As shown in Figure 1, the design suite provides an entirely new approach that achieves optimum RF closure through a unified data model and design environment encompassing all of the design domains. The data model is high-frequency aware, permitting accurate extraction and modeling of all design elements, including active and passive devices as well as interconnects at high frequency. The new solution is built on an open, standard-based software platform, enabling easy integration of the most capable, best-in-class tools to capture, synthesize, simulate, optimize, layout, extract, and verify designs in all domains. The Analog Office design suite is fully integrated into existing digital and mixed signal IC design flows and enables analog and RFIC design engineers to significantly shorten their development cycles and speed wireless products to market.

Complete Front-to-Back Analog and RFIC Design System
Traditionally, EDA tools separate the electrical design/analysis and physical implementation, and provide poorly integrated tools for different design tasks. The Analog Office 2004 unified design environment, on the other hand, fully interacts with a comprehensive and powerful set of integrated tools for top-down and front-to-back analog and RFIC design. The toolset spans the entire IC design flow, from system-level to circuit-level design and verification. An easy-to-use graphical user interface supports system- and circuit-level design methodologies, electrical and physical design, schematic capture, simulation/analysis, layout and verification, frequency- and time-domain simulation and analysis, and links from design to test. The integrated waveform display and analysis capabilities support complex RF measurements, including hundreds of pre-built measurements, parametric tuning, noise analysis, sweep parameter analysis, multiple test benches with multiple simulators, statistical analysis, and optimization.

A variety of simulation types are offered, including system simulation with AWR's Visual System SimulatorT (VSS), time-domain simulation with Synopsys' HSPICE®, frequency-domain simulation with AWR's harmonic balance simulator, and electromagnetic simulation with AWR's EMSightT tool. The open platform provides integration through a SPICE socket for third party SPICE-based circuit simulators and AWR's EM SocketT interface for third party EM simulators.

The software also offers a powerful and easy-to-use physical design suite with a fully interactive layout editor supporting polygon editing and parameterized layout cells, automated device-level placement and interconnect routing, an integrated and interactive design rule checker (DRC), and 3D full field solver-based extraction with industry gold standard, high speed extraction technology from OEA International.

Figure 2: Analog Office 2004 software offers an interconnect-driven/RF-aware methodology that focuses on accurate RF interconnect modeling and analysis throughout the entire RFIC design.

Concurrent Interconnect-Driven/RF-Aware Design Methodology
Analog Office 2004 software offers an industry-first interconnect-driven/RF-aware design methodology built around AWR's Intelligent NetT (iNet) technology. Similar to timing-driven or wire-driven digital design methodology, the interconnect-driven/RF-aware methodology focuses on accurate RF interconnect modeling and analysis throughout the entire RFIC design process to reduce or eliminate design iterations, shorten the design cycle, and ensure first-time design success (Figure 2). Unlike existing net constructs built on a "digital-centric" data model, the Analog Office 2004 iNet technology is based on an RF-accurate net model with multiple levels of abstraction - "short-circuit," lumped RLC, distributed and coupling resistors, inductance, RLCK, fully distributed transmission line, or full 3D EM models -using a single environment and data model. iNet technology provides concurrent and real-time physical modeling of RF interconnects while the layout is in progress, eliminating the need for a serial post-layout connectivity extraction step. Simulation and analysis can be invoked immediately to verify the performance of the design as soon as the critical nets are laid out, without waiting for the rest of the circuit to be completed, ensuring early and complete RF design closure.

Figure 3: A new measurement-driven paradigm provides efficient parametric
design over multiple test benches and simulators, shortening design time.

Measurement-Driven Paradigm
The traditional EDA method requires that designers undergo multiple design setup steps to obtain a particular analysis result from a selected simulator. This cumbersome process results in the generation of many data files that require long simulation times and consume large amounts of memory. AWR has pioneered a new, yet more natural, paradigm for high-frequency design that simplifies this process. As demonstrated in Figure 3, with the Analog Office 2004 product, users simply set up multiple test benches and analysis measurements ahead of time (similar to a specification sheet) and then set up the parameters for the designs. As soon as the simulation is started, the system automatically selects the "right" simulator for the particular analysis, extracts the "right" models for the design elements, runs the simulator(s), obtains the results and processes them into requested measurements, and presents the results in multiple graphs and tables. In the same environment, users can dynamically "tune" the design quickly and efficiently across a set of parameters, test benches, and simulators.

Powerful Analog and RF Simulation Technologies
AWR has developed one of the industry's fastest harmonic balance simulators, which performs 10 to 1000 times faster than similar products for most problems. This superior simulation performance is coupled with proprietary convergence algorithms that extend the capacity of the simulator to handle large and highly nonlinear circuits. The speed and capacity of the simulator, as shown in Figure 4, can also open designs up to more rigorous statistical modeling and yield analysis, which now become practical on circuits that may have consumed too much simulation time in the past.

The Analog Office 2004 time-domain simulator is able to solve unique problems such as those found in phase-locked loops or oscillators during start-up conditions. An optional time-domain engine, which augments the harmonic balance, Voltera and EM simulators, is integrated with Synopsys' golden standard HSPICE, which provides the fastest, most accurate, highest capacity simulations, as well as hundreds of foundry-proven built-in device models for most commercial IC foundries.

Figure 4: The detailed design and analysis results shown for a power amplifier, including gain vs. power, pout vs. pin, and load pull data contour, are possible with faster, more powerful simulation technologies.

Physical Layout with Automatic Placement and Routing, Integrated DRC and Embedded 3-D Extractor
Analog Office 2004 design suite provides IC designers with a complete physical design system to fully implement their analog and RFIC designs within a single environment, eliminating the need for switching between multiple environments and databases.

A fully interactive custom layout tool with integrated device-level, auto-placement and auto-routing features speeds up the creation of analog and RF circuit blocks and chips. A fully integrated DRC ensures the physical layout being created always meets the process design rules, resulting in a correct-by-design, error-free layout. The layout editor is directly connected to the EM socket, providing "on-the-fly" EM extraction and modeling of arbitrary layout structures and complex spiral inductors. At every step during the physical design process, the iNet technology continuously updates in real time the underlying interconnect data model, and as soon as after each interconnect is "implemented" or laid out, concurrent simulation and analysis can be immediately invoked on schematic or layout to verify the performance of the overall design without waiting for the final layout of the whole design to be completed.

To ensure proper modeling of inductance coupling between nets in gigahertz physical layout, the software also provides the Cheetah 3-D field solver, the core interconnect extraction technology from OEA International's NET-ANT 3D critical multi-net field simulator. The selected net or nets are automatically extracted and modeled as distributed RLCK for fast and accurate simulation. This level of interconnect modeling compliments other modeling levels that are managed by iNet technology, such as lumped RLCs, and fully distributed transmission lines, thus extending the designer's range of design trade-off flexibility between simulation run-time performance and modeling accuracy.

Figure 5: Open, stand-based process design kits support popular silicon foundries for an efficient and error-free RFIC design flow.

Open, Standard-Based PDKs Support Popular Silicon Foundries
The integrity of the electrical and physical model data is often a contentious issue between foundry customers, foundries, and EDA vendors. Neither an EDA company nor a foundry can deliver an optimal process design kit (PDK) in isolation. Initially driven by mutual customers, AWR has established close partnerships with leading RFIC foundries to develop and deliver validated PDKs for SiGe, BiCMOS, and RF CMOS processes that include integrated electrical models, including schematic symbols and simulation models, parameterized layout cells, and DRC files, as shown in Figure 5. The AWR PDKs enable an efficient and error-free RFIC design flow. End users, commercial foundries, and EDA vendors can all benefit from the reduced support effort, higher customer satisfaction, and shorter design cycles that result from integrated foundry libraries.

Seamless Integration with Mixed-Signal IC Design Flows
Analog Office 2004 design suite can be used to design the entire chip from system-level modeling and simulation through to final layout and tape-out. The software will generate the necessary industry-standard files, such as layout vs. schematic (LVS) netlist and GDSII, to interface to a final verification flow based on industry-popular IC physical verification tools from Mentor Graphics, Synopsys, and Cadence.

AWR is actively working with the OpenAccess standards organization to ensure a smooth path between Analog Office 2004 design system and an OpenAccess-based Cadence design flow. The resulting integrated flow is similar to the current Analog Office and Cadence Design Framework II integrated flow, except that OpenAccess is now the common database.

Conclusion
The demand for complexity and efficiency of size and power consumption in modern communications applications is driving the need to achieve complete RF closure in a design in order to ensure validity before commitment to implementation. Multiple design cycles are costly not only in terms of manpower and hardware, but, even more importantly, slips in product schedules can be devastating in terms of competitive edge. Analog Office design suite provides a modern, efficient solution with the unique ability to streamline the RFIC design process by combining within a unified, easy-to-use environment both system- and circuit-level design phases. This includes both time- and frequency-domain simulation capabilities, as well as models, libraries, and measurements that are completely compatible and seamless between those system and circuit design phases and the frequency- and time-domain engines. Analog Office 2004 answers the need for a new and highly integrated EDA solution to address the complex issues inherent in the design of next generation high-performance wireless communication products.

APPLIED WAVE RESEARCH, INC.