Highest Performance DSM PLL for Space and Military Applications
By Gary Wu, Senior Engineer of Space Products, and Ron Reedy, Founder, CTO, Peregrine Semiconductor Corporation

Satellite communications have continued to grow in the post-Iridium era.They are being launched at increasing annual rates for military and commercial uses, and for established and developing countries. The cost of design, construction, and launching, not to mention the spectral allocation for one satellite are very high compared to any other single communication infrastructure. As a result, the satellite must be incredibly efficient in the obvious categories of power, weight, and reliability, but it must also be incredibly high performance to maximize the spectrum and transponder data throughput.

Modern high performance communications systems used in satellite applications have evolved to very large payloads with more than 100 transponder channels. The satellite requirements naturally flow down to increasing pressure on integrated circuits to meet increased performance, power consumption and lower system price. The components used in such systems are also applicable to the difficult performance and reliability requirements of military systems. Radiation performance, both single event and total dose, must be guaranteed while meeting the highest reliability standards of any application. To meet these demands, Peregrine Semiconductor has further engineered its industry-dominant line of UltraCMOST Phase Locked-Loop synthesizers (PLLs), resulting in a significant leap forward in performance. In this article we discuss UltraCMOS technology process basics, revealing the resulting performance of a new delta-sigma modulated (DSM) PLL delivering normalized phase noise of
-216 dBc/Hz, which is the lowest phase noise available in any such fractional-N DSM PLL. Further, unique architectural attributes allow for digital modulation of these devices, creating complex, flexible systems without direct digital synthesis (DDS) devices.

Background
Satellite communications are considered among the most reliable and flexible communications systems available. Once on line, they are immune to terrestrial issues such as weather or physical interruptions. High demand for the most useful frequencies places stringent requirements on providers to deliver highly efficient systems utilizing advanced technologies and architectures. For example, satellites were among the earliest uses of spread spectrum techniques.

Satellites also place the most stringent requirements on size, weight, cost and reliability. Once launched, satellites orbiting at up to 23,000 miles altitude do not receive repair visits. Attaining power, cooling and radiation requirements for these applications -- designed for 15 years of autonomous operation -- has led satellite manufacturers to seek unique solutions that often become standards.

Peregrine Semiconductor has provided such unique solutions for more than a decade, including high-performance PLLs, prescalers, RF switches, digital step attenuators and highly integrated rad-hard ICs. The company's advanced silicon-on-sapphire process technology enabled further performance milestones, including the reduced phase noise of the DSM PLL, while increasing architectural flexibility. Further, using digital techniques, it is possible to create information bandwidths comparable to, and even exceeding, the loop bandwidth of the complete locked loop.

UltraCMOS Technology
As shown in Figure 1, UltraCMOS technology combines 100 nm thick Si film and a sapphire substrate, enabling fully depleted CMOS ICs.

Advantages of this technology for RF and mixed-signal applications include the following:

• Low capacitance, high-speed digital at low power
• Fully depleted operation, exceptional RF linearity, speed, and low voltage performance
• Excellent RF performance:
> fmax typically 3X ft (43 GHz at L = 0.5 mm; and 100 GHz at 0.25 mm)
> very high linearity
(+38 dBm IP3 mixers)
> high Q integrated passives
(QL > 40 at 2 GHz or 5 nH
inductor)
> an extremely low-loss substrate at RF frequencies
> port-to-port isolation
(>80 dB @ 216 MHz)
• Integrated EEPROM available without additional masks or process steps
• Multiple threshold options without additional cost
• Inherent radiation hardness
• Standard CMOS design techniques including high density digital CMOS
• Up to 4kV HBM ESD protection with low parasitics
• Processed in standard CMOS facilities

Phase Locked-Loops
Figure 2 shows a block diagram for an Integer-N phase locked-loop. Integer-N PLLs are typically limited because they create only those frequencies which are determined by the integer ratio between the VCO frequency and the phase detector frequency. By rapidly jumping between adjacent integer values, Fractional-N PLLs can create frequencies a fraction of the way between adjacent integer values. Such devices not only improve frequency resolution, but also create fractional spurs which are more complex to filter than those created by Integer-N PLLs.

Recently, the fractional-N concept has been taken to the next level of complexity and performance in the delta-sigma modulated (DSM) PLL. In this design, the PLL is hopped in a pseudo-random fashion among a multiple of integer frequencies, as shown in Figure 3.

As shown in Figure 4, a multi-stage noise shaping (aka "MASH") digital engine dithers the PLL frequencies of Figure 2 to shape the spurious noise above the loop filter bandwidth, where the loop filter can efficiently suppress it. The result is that DSM PLLs allow very small step sizes at very low phase and spurious noise.

By optimizing all blocks for minimum phase noise (called "jitter" in the time domain), Peregrine's PE97632 exhibits 5-10 dB improved phase noise over its predecessor, PE9763. Figure 5 shows phase noise vs. carrier offset for the new PE97632, which is approximately 10 dB improved at 100 Hz offset and 5 dB improved at 10 kHz offset. For the test conditions, phase noise referred to the phase detector is -216 dBc/Hz, which is among the lowest values reported to date by any device, including those not qualified for satellite operation.

Direct Modulation Application
By adding additional modulating data as digital information to the MASH network, as shown in Figure 6, the PLL can be made to impress the desired information and onto the carrier. The resulting system is a direct digital upconverter which contains only two components: the PLL and VCO. Essentially, the information is a form of noise shaping in which the noise is the desired information. Output from the VCO can be injected directly into a power amplifier chain for transmission.

Conclusion
The newest satellite and military applications are not only requiring increased complexity, functionality, flexibility and performance, they are also demanding exceptional levels confidence to accomplish 15+ year missions. Highly integrated RFICs are proving to be exceptional solutions to these and other design challenges, and Peregrine's newest low-phase-noise DSM PLL is one such example. With phase noise improvements of 5-10 dB and a novel approach for direct digital modulation, the DSM PLL/VCO combination delivers levels of integration and performance to simultaneously drive system value and reliability, the ultimate goal of any RF engineer.

Reference
1. For example, see www.psemi.com for space PLL products.
2. R. Reedy & M.C. Comparini, "Perspective of RF CMOS/Mixed Signal Integration in Next Generation Satellite Systems," EuMW 2003.

Peregrine Semiconductor Corporation
www.psemi.com
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