Waveshaping for High Power Class “C” RF Amplifiers
By Peter Petropoulos, Engineering Manager, Technical Services Laboratory Inc.

Abstract
High power pulsed amplifiers have found great demand in today’s spread spectrum communications, ranging in applications from JTIDS, TACAN, IFF and radar in the military sector to DME and TCAS in the commercial sector. The bandwidth and harmonic content of the frequency spectrum transmitted is of major importance for successful signal decoding. Class C amplifiers are often selected for transmitters over CW types due to their inherent high efficiency and their ability to use solid state devices capable of operating at high power levels at low and medium duty cycles. A typical disadvantage in using class C amplifiers over their CW equivalents is the inability to effectively control the performance characteristics, such as the rise and fall times of the modulating pulses. Depending on the operating transmission system, the requirements for the time response of these parameters can range from a linear time control ramp to a sinusoidal form or a Gaussian distribution pattern. Several efforts have been made in the past to control these parameters with such techniques as “diode clipping,” “collector modulation” and “output attenuation.” Each of these previous methods has limited success in certain cases but can not be utilized over a wide application of frequencies and power levels.

This paper presents a method of an effective control method utilizing feedback and an LDMOS (Laterally Diffused Metal Oxide Semiconductors) device to successfully control the output wave shape of a high power pulsed Class C amplifier. It further examines the required bandwidth to achieve the desired goals and presents methods to synthesize networks for maximum bandwidth based on Bode’s second criteria for stability and Foster’s synthesis equations. An application example is presented for a high power DME amplifier and all relevant mathematical derivations are presented for reference.

Background
Class C amplifiers are used virtually in all applications requiring high power pulsed amplifiers. These amplifiers are implemented primarily by the use of bipolar common base N- type transistors. The frequencies range from several MHz to 3300MHz and include the L-Band and S-Band domain. Power levels with single output devices are in excess of 1KW, while parallel configurations can result in levels up to several kilowatts. The lineup of these amplifiers is typically made up of a MMIC (Monolithic Microwave Integrated Circuit) front end device and is followed by several stages of amplification depending on the final output power stage. The requirements of the output RF envelope vary depending on the application. IFF (Identification Friend or Foe) designs require an input rise time control in the range of 50 to 100ns and a fall time less than 200ns. DME (Distance Measuring Equipment) designs require an output RF envelope resembling a Gaussian distribution. Some designs require AM modulation as well as fast attenuation for pulse to pulse level control.

The conventional class C type pulsed amplifier has an inherent problem with any of the above requirements. The output characteristics of the RF envelope depend on the transistor type used and its compensating network and do not respond to any input variations. To deal with the problem, designers have used several methods for controlling, to a limited extent, the wave shaping. One of the popular techniques used is the “clipper diode” method. This design utilizes a high power pin diode, usually in the shunt configuration, at the input of one of the final stages that controls the rise and fall times of the pulse by means of appropriate control circuits. This control method is not always successful and it requires tuning the diode to the circuit to which it is “launched.” Furthermore, when the amplifier is used for more than one frequency, the problem becomes more complex; it is difficult to tune the diode for proper performance at all frequencies and results in loss of output power due to input mismatch.

Other methods that are being used for control also have similar limitations, plus the fact that none of these methods is capable of producing complex waveforms and control attenuation.
The design presented in this paper deals with all of the above limitations and results in a circuit that is effective in controlling the output RF envelopes and producing complex signal waveforms that otherwise would be possible only by linear amplifiers.

Issues
Local feedback control is familiar to all engineers who deal with analog designs and certainly is the proper method for optimizing linear amplifiers as well as being applied in servo mechanisms and several other control applications.

The basic concept in this design was to use feedback to control the envelope of the output RF waveform by using some voltage reference and a signal derived from the RF output envelope, feed it into an error amplifier and therefore, control the output wave shape. The basic concept was simple enough but there were several problems associated with it. First, an appropriate control element had to be found that was linear enough and had substantial bandwidth so as not to produce phase shift at the frequencies of interest, at least several MHz. In the case study chosen, the rise time requirement was approximately 1us. For monotonic systems with all poles and zeros located on the negative s- axis of p-plane, W. C. Elmore1 has related the rise time and BW as tr=2.5/?0 where ? is the angular cut off frequency; therefore, a minimum gain bandwidth around 2.5MHz was necessary. Initially, several control techniques were evaluated including variable attenuators, but none resulted in an acceptable control element.

The advent of high power LDMOS at the frequencies of interest was the ultimate solution to this problem. It provided a gate for suitable control and high output power that can be installed as one of the output stages. Another issue was the choice of a linearized detector which can track the output RF for at least 30dB dynamic range so that it can provide the correct input to the error amplifier. A special “zero biased” Schottky detector diode was chosen that met our performance objectives.

Design
The design was based on TSL’s model 1411, 1.2KW amplifier part of Series 1400 amplifier/calibrators for DME and TACAN applications, requiring fine resolution in RF output attenuation steps and precise waveform control.

Figure 1 is a simplified diagram of the approach taken for the design described below.

This design presented the most difficult challenge due to its Gaussian output wave shape requirements, attenuation steps and high power output (several amplifier stages). The critical parameters of this amplifier were set as follows:

Frequency range: 960MHz to 1215MHz
Input power: 0dBm
Output power: 1200Watts
Type of output waveform: Gaussian
Rise time: 1us
Fall time: 2.5us
Pulse width: 3.5us
Output power control: 0.5db attenuation steps
Duty cycle: 3% maximum
Weight: < 25lbs

The amplifier is made up of six (6) RF stages; see Figure 2. Stages A1 through A4 make up the low power driver. The output of stage A4 is divided in two by a Wilkinson splitter with power levels each suitable to drive the next stage. The following amplifier stage, A5, which is also where the control signal is injected, is made up of two LDMOS power transistors with an output of 53dBm each. Finally, the last stage, A6, has four power bipolar power transistors with a maximum combined output power in excess of 1200 Watts.

First, the critical Open Loop Gain/Phase response of the amplifier for the last two stages was measured in order to determine the loop bandwidth and thus, the ability of the system to control the rise and fall times of the expected waveforms (Table 1). Measurements were made over the entire operating frequencies of the amplifier between 960MHz and 1215MHz; the data varied some depending on the test frequency of the amplifier. The frequency selected for analysis was 1100MHz, which displayed the maximum phase shift. This data indicates that a 1800 phase shift occurred around 4MHz. Analyzing the results, we determine that the significant time constant of the loop was due to the combination of the LDMOS gate capacitance and the driving impedance of the control gate. Typically, the gate capacitance of these power devices is approximately 300pf to 400pf. The input impedance is made up of the resistor connecting the gate to the error amplifier, plus the output impedance of the amplifier itself (approximately 120 Ohms.)

In order to maximize the response of the system, we refer to the theory of “Bode’s Ideal Loop Gain” characteristics2 .This plot is shown in Figure 3.

Using a semi–empirical method and the phase gain data taken from the RF amplifier stages, a plot was drawn for the optimum loop response. The low frequency gain was estimated based on the accuracy of the output waveform to be approximately 40dB. This plot indicates that the best gain bandwidth we can expect is around 3MHz, sufficient for the expected rise time of 1us.

This figure demonstrates the application of Bode’s Ideal Loop Gain characteristics in maximizing the bandwidth of a given amplifier. This method is demonstrated by a paper presented at the International PCI conference3. A brief explanation is given below.

A curve is drawn from the unity gain intersect at 12MHz to 3MHz and from there, a new asymptote is drawn with a slope of 10dB/Oct. The start of this asymptote depends on the phase margin that is desired as well as the additional phase shift that may occur due to the final asymptote. We observe that the low frequency break occurs at approximately 100KHz and at 1MHz the loop gain is in excess of 10dB. Foster’s network synthesis4 or other methods can be used to derive the appropriate pole – zero compensating circuits.

Another method to improve the open loop bandwidth is to substitute the resistive impedance with a fixed inductor and this method should be used when dealing with fast rising waveforms such as the requirements for IFF.

Simulation
Micro-Cap simulation software was used to analyze the given design.
A three stage amplifier was constructed using Linear Technology’s dual high speed operational amplifier LT1364. Individually, these amplifiers have an open loop bandwidth of 80MHz with the first pole occurring at approximately 10KHz. Based on the desired gain, local feedback was used with each stage, which set the first pole of stages V1 and V2 at about 2MHz.

In reference to Figure 5, the first stages (V1 and V2) make up the error amplifier. The last stage (V3) is a buffer/amplifier. E1 is a Laplace transfer impedance with characteristics similar to the response of RF amplifiers stages A5 and A6, the LDMOS stage and the final bipolar transistor stage (Table 2).

The amplifier was compensated based on the above criteria that approximate Bode’s Ideal Loop Gain slope and an open loop AC analysis was carried out. The results of this analysis are shown in Figure 4. As can be observed from this figure, unity gain crossover occurs at about 2.5MHz and there is 16º phase margin for a stable amplifier which results to a stable amplifier.

Figure 5 shows the complete simulated amplifier. U1 is a Gaussian waveform source that is generated for reference by using Micro-Cap’s user source. The output level of the reference is set at 1 Volt peak.

Figure 6 shows the transient response of the circuit. As can be seen here, a two pulse Gaussian waveform type is generated at the output of the circuit, which is in close proximity to the reference waveform presented at the input.

Circuit Details (Figure 7)
Amplifiers U7A and U7B are “op-amps” which sum and invert a signal generated by an FPGA. The incoming signal is a dual pulse Gaussian distribution waveform spaced 12us apart, in accordance with DME equipment requirements. U8 is a variable gain amplifier used to control the amplitude of the reference waveform. Op-amps U10B, U10A & U9A are the error amplifier stages as presented in the simulation section above.

RF feedback is received at the terminal “FWD PWR IN” and compared with the reference at U10B. The output of the first stage is further amplified by U10A and U9A and finally, it splits into two lines and feeds the LDMOS transistors that make up the driver stage to the final power output stage. The range of the gate signal required for the control of the LDMOS transistors under consideration is between –2.0V and +4.0V. The excursion of the output level at P3 should be limited to this range, otherwise the drain current Id of the devices may rise substantially, causing a device failure.

Figure 9 shows the actual resulting output RF envelope. As can be derived from this figure, the output RF envelope closely tracks the voltage reference. The rise time is approximately 1.5us and the fall time is 2.5us. These specifications were derived from the ICAO ANNEX 10 for DME requirements.

Figure 10 shows a case where a series of half sine waves of different amplitudes from 100% (0dB attenuation) to 10% (-20dB attenuation) of the RF power are used as a voltage reference and demonstrates how the output RF envelope tracks the input reference.

Table 3 is the output power data taken over the entire operating frequency of the amplifier between the frequencies of 960MHz and 1215MHz. It can be seen that the output peak power level is constant within +/-0.30dB.

For the purpose of maintaining linearity throughout the dynamic range of the amplifier, some power margin should be allowed near its maximum power. Typically, 0.5dB margin is sufficient so the amplifier does not operate at the heavily compressed gain region.

Conclusion
The method proposed in this article of using feedback to control the behavior of the output RF envelope of class C power amplifiers effectively, and without losing efficiency or output power level, was proven to be attainable. The main task in this process is to select an appropriate device which provides a method of control of the RF power level, with wide enough bandwidth to accommodate the design objectives. In the design presented here, a six-stage class C, RF power amplifier was designed. A 250Watt power LDMOS transistor specified over the operating range was selected as the control element followed by four (4) bipolar transistors configured in parallel for a total output power of 1200Watts. The output waveform envelope of the amplifier was controlled by a three stage error amplifier and by the LDMOS transistor gate. The amplifier selected was “linearized” up to a frequency level of interest and responded well to AM modulation with complex waveforms. The power efficiency of the amplifier was the same as any other comparable Class C amplifier. The output power level of the amplifier was controlled effectively over 24dB range.

The output power of the amplifier was constant within 0.3dB over the entire operating frequency of the amplifier.

The amplifier was housed in a 19" rack for universal AC power requirements. The total weight of the unit was 22lbs, which met our design objectives. An airborne version of this amplifier was also designed, packaged in an envelope 5"x7"x1.7" supplied by DC inputs instead of an AC bus.

Model 1413 2.5KW amplifier/calibrator, which has the same design as the one described above, is shown in Figure 8.

With the advent of higher power LDMOS transistors and other devices with higher power capabilities, the bandwidth of the amplifiers can be maximized to design these type amplifiers with rise and fall time requirements faster than 100ns and output power levels in excess of 3KW.

References
1 Elmore W. C., “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., 19, 55 (1948).
2 Hakim S. S., “Feedback Circuit Analysis,” London Iliffe Books Ltd 1966.
3 Petropoulos P. P., “Optimizing the Loop Response of High Frequency Power Supplies,” PCI Proceedings March 1982.

TECHNICAL SERVICES LABORATORY, INC.

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