Simplify Data Acquisition with an Ultra Wideband High Linearity Track-and-Hold Amplifier
By Michael Hoskins, Principal Design Engineer; and Jon Firth, Marketing Engineer; Hittite Microwave Corporation

Wideband data acquisition systems encompass a wide variety of applications from software defined radio to real-time digital radar systems. A goal in many of these systems is to simplify and minimize the complexity of all of the stages from signal acquisition (antenna) through digitization of the data stream prior to sending the bit stream on for further digital processing. Ideally, the antenna would be directly connected to a large dynamic range analog-to-digital converter (ADC).

In wideband data conversion, a Track-and-Hold Amplifier (THA) is often used within the ADC or as a separate component preceding it, to condition the signal for acquisition by the converter. The THA’s function is to sample the input signal at a precise instant and hold the value of the sample constant during the analog-to-digital conversion process. This results in signal sampling by one low jitter sampler and it reduces the ADC’s dynamic linearity requirements. Since the linearity of the ADC is usually degraded at higher input signal frequencies by slew rate dependent distortion effects, a THA can reduce ADC distortion by providing low slew rate, constant amplitude signals to the ADC during sampling. For this reason, a high linearity, wideband THA can often improve the linearity performance of ADCs in wideband applications such as radar, signal intelligence, and digital receivers for communications.

Hittite Microwave has developed the HMC660LC4B Track-and-Hold Amplifier, the first of a new family of wideband Track-and-Hold Amplifiers, providing unparalleled linearity for an ultra-wideband device. The HMC660LC4B allows designers to directly sample full-scale 1 Vpp signals with up to 4.5 GHz input bandwidth, and up to a 3 GHz clock rate (see Table 1.) For input signals in the DC to 4 GHz band, and a clock rate of 2 GHz, Hittite has measured an impressive 9-bit track-and-hold mode linearity at 1Vpp input level, offering a significant improvement over the nearest competition.

The HMC660LC4B THA is available in a compact 4 x 4 mm leadless, surface mount RoHS compliant package. The device may be used in conjunction with high-speed ADCs to simplify the downconversion signal path in many digital receiver architectures. The THA in front of the ADC can effectively be driven with a signal at a higher intermediate frequency, so that designers can eliminate mixers, band-pass filters, amplifiers, and local oscillator functions to reduce power and complexity while increasing overall system reliability. The HMC660LC4B is suitable for many applications including digital sampling oscilloscopes, software defined radio, military and commercial radar systems, EW, ELINT, direct microwave/RF/IF sampling, microwave/RF/IF peak detection and power measurement, wideband spectrum analyzers and RF/IF/fiber optic test systems.

Fabricated on a SiGe BiCMOS process, the HMC660LC4B employs a novel design topology which allows a significant improvement in the tradeoff among bandwidth, linearity, and hold-mode feedthrough. The new topology also overcomes the problem of input bandwidth sensitivity to input signal level, which is a common problem in other commercial track-and-hold circuits. While other wideband THAs often exhibit a 33% bandwidth loss between one-half full-scale and full- scale input levels, the HMC660LC4B bandwidth remains constant up to full-scale input.

The HMC660LC4B’s internal architecture comprises several key functions: input amplifiers to process the input signals and the clock signals, a track-and-hold switching core, and an output amplifier. Differential input, clock and output signals are used in the design to help minimize power supply, ground and radiated noise.

Differential input signals are applied to the IN+ and IN- terminals of the HMC660LC4B (Figure 1) and are fed into the input amplifier, which buffers the differential input signals which drive the Track-and-Hold (T/H) switch core. The clock input signals (CLK+ and CLK-) are fed to a clock driver to provide the fast clock edges necessary for high-speed sampling at the Track-and-Hold core. After sampling, the held signals are buffered through an output amplifier and appear as differential output signals (OUT+ and OUT-), each of which is capable of driving a 50 ohm impedance level.

The HMC660LC4B is designed to deliver ultra clean output waveforms with minimal glitches. This provides the ADC with a well conditioned signal which is easier to digitize accurately. Figure 3 shows measured time domain output waveforms for a HMC660LC4B displayed on a Tektronix TDS8000 sampling oscilloscope. The input signal is 1Vpp with an input frequency of 3.125 GHz, and the clock rate is 500 Msamples/second (MS/s). The blue trace shows the HMC660LC4 in track mode, and the red trace shows the device in track-and-hold (sampling) mode. Note that the small ripples in the hold portion of the waveform are caused by reflections on the 2 ft. cable connection between the HMC660LC4B evaluation board and the Tektronix TDS8000 sampling oscilloscope. When used with an ADC, the THA should be located in close proximity to the ADC to minimize the time duration of any reflections.

Figure 4 shows that the spurious free dynamic range (SFDR) of the HMC660LC4B is limited by the 2nd order effects to about 61 dB (9.9 bits) with an input signal of 0.5 Vpp (one-half full-scale) at 4 GHz, clocked at 1 GS/s. This linearity performance is significantly better than the closest competing track-and-hold device, which only provides typical SFDR of 32 db (5.05bits) with a 4 GHz, 0.5 Vpp input signal, clocked at 1 GS/s.

Another important feature of the HMC660LC4B is that it exhibits proper linearity order dependence. This is particularly important for designers who are employing signal averaging using digital signal processing (DSP) techniques. Such users may perform averaging to reduce the wideband noise floor, and may choose to trade off input signal levels to obtain much higher linearity. For example, using the HMC660LC4B with one-half full-scale input signal level of 0.5 Vpp at 4 GHz, (versus a 1 Vpp full-scale input signal at 4 GHz), and a clock rate of 1 GS/s, the linearity will improve by 6 dB from 55 dB to 61 dB. Similarly, with a full-scale input signal of 1 Vpp at 1 GHz, and a clock rate of 1 GS/s, the linearity will improve by 12 dB from 54.6 dB to 66.6 dB if the input signal is reduced to 0.5 Vpp at 1 GHz.

HMC660LC4B also exhibits 65 fs of sampling aperture jitter, and the hold-mode feedthrough rejection is better than 60 dB. The device exhibits a maximum time domain noise value of 1.1 mV rms integrated over the full 7 GHz output amplifier bandwidth. This wideband output amplifier contribution to the total output noise is substantial. If desired, a significant reduction in output noise can be achieved by filtering the output to a lower bandwidth. This is particularly effective if the device is operating at lower clock rates, e.g. 500 MHz, where the extended settling time of a bandlimiting filter still falls within the hold time (typically one-half of a clock period). For example, if the output is filtered with a 1 GHz bandwidth single pole filter compatible with 500 MHz clock rate, the signal-to-noise ratio can be improved by approximately 7.5 dB from 50.5 to 58 dB. The output filter has little impact on the sampling bandwidth because the output waveform is a series of held samples, which represent the input signal heterodyned to baseband by the sampling process.

These specifications are essential for designers who are looking to improve and expand the capability of commercially available high speed ADCs. The HMC660LC4B may be used as a subsampling front-end for lower speed 12-bit, 300-500 MS/s ADC modules. For example, Atmel’s 12-bit, 500 MSPS ADC module, the AT84AS001TP, would fall into this category. Adding the HMC660LC4B Track-and-Hold Amplifier to a lower bandwidth ADC allows the ADC to subsample a fairly broadband signal (for example, 1 GHz centered at 3.5 GHz) and then directly convert (or alias) it to baseband frequency for conversion by a lower-speed, high-resolution ADC.

When used with lower sample rate converters, the HMC660LC4B can provide an extension of input sampling bandwidth. When used with higher sample rate converters, the THA can provide improved high frequency linearity. For example, the linearity of even the highest speed, state-of-the-art AT84AS008 Atmel converter starts to significantly degrade above 2 GHz, and linearity is not specified above this frequency, even though the device supports an input bandwidth of 3.3 GHz. Since the full-scale input for this converter is 0.5 Vpp, the HMC660LC4B would operate at half-full-scale in this application (SFDR ~60 dB or better over the input band) and could provide both a bandwidth extension to 4.5 GHz, as well as improved high frequency linearity when used with this type of converter.

Summary
The HMC660LC4B’s combination of wide bandwidth, high linearity, and excellent isolation provides a unique solution for high-speed ADCs serving a myriad of applications including digital sampling oscilloscopes, software defined radio, military and commercial radar systems, EW, ELINT, direct microwave/RF/IF sampling, microwave/RF/IF peak detection and power measurement, wideband spectrum analyzers and fiber optic test systems. The HMC660LC4B THA facilitates direct conversion from RF or high-IF signals, eliminating intermediate mixers, amplifiers, filters, and local oscillators to reduce system size, power, and complexity. Both the HMC660LC4B product and the evaluation kits are available from stock. Complete product specifications may be found at www.hittite.com.

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