|
Low
Skew, 250 MHz 1.2V-2.5V Clock Buffers for Reference Clock
Distribution in Low Power Networking Applications
By Kay Annamalai, Pericom Semiconductor Corp.
The clocking requirements for most electronic
systems can be achieved through a lower frequency external
reference, and then internally, this reference gets multiplied
to the required frequency for applications such as serial
connectivity, internal CPU, memory or peripheral clocks.
As the multiplication factor gets larger and the internal
clock frequency becomes higher, there are stringent requirements
imposed on the external clock reference including skew,
duty cycle, clock delay, output jitter, phase noise, and
voltage level. This article outlines the importance of these
parameters to the system design and how it can be achieved
through low voltage clock buffer offerings from Pericom
Semiconductor.
Clock Distribution for the Network
Infrastructure
Figure 1 shows the basic blocks of the
network switch infrastructure, consisting of several switch
ports that connect to the end nodes. The major blocks are
the switching fabric, the Media Access Control layer (MAC),
Physical layer (PHY) and Physical Medium Dependent layer
(PMD). The external timing reference gets distributed to
the switch fabric and switch ports. An example of the timing
reference distribution for the PHY layer of GE switch is
shown in Figure 2. Here, one timing reference
is generated using a clock generator with an external crystal
and distributed to the N PHY ports by means of RCLK1, RCLK2
and RCLKN. Internal to the PHY ports, the RCLKs are used
to generate the high-speed serial clock by means of a clock
multiplier inside the switch PHY ports.
The key parameters of the external reference clock (RCLK)
to the network switch PHY ports are:
a. Phase noise power expressed as dBc/Hz over the frequency
offset of interest from the center frequency of RCLK (e.g.
1MHz-20MHz),
b. Phase jitter expressed as rms value over a certain frequency
interval (e.g. 1MHz-20MHz)
c. Output to output skew
d. Output duty cycle as percentage
e. Input/output levels
f. Output rise/fall times
g. Power consumption
The significance of each of these parameters is as follows:
Phase Noise (dBc/Hz): This indicates the
frequency response characteristics of RCLK. This number
should be low for high-frequency networks, such as Gigabit
Ethernet, as this translates to output waveforms with best
signal integrity (i.e. reduced noise and better system margin
for link distances and bit error rate). The lower frequency
limit to consider for the phase noise power response is
determined by the loop bandwidth characteristics of the
Clock and Data Recovery circuit (CDR) in the PHY silicon.
So, the phase noise for frequency offsets less than the
loop bandwidth is reduced by the CDR. Upper frequency limit
for phase noise power is determined by the cutoff frequency
for the low pass filter response of the Clock Multiplier.
Phase Jitter (rms): Lower phase noise will
translate in time domain to reduced phase jitter and hence,
increased eye opening. The effect is same as Phase jitter.
Both Phase jitter and Phase noise are usually specified
at the same time so that the individual contributor to the
phase jitter can be better understood.
Output to Output Skew (ps): This parameter
becomes important for synchronous designs. For the example
shown in Figure 2, RCLK is used both to
clock out data from MAC as well as to clock in data from
PHY. So, as RCLK becomes higher in frequency, the clock
cycle time becomes smaller and, as a result the timing margin
for the system design is impacted by the output to output
skew - smaller the skew, the bigger the margin for the system
design.
Output Duty Cycle (%): Output duty cycle
is the % ratio of HIGH time to LOW time. This becomes significant
for high frequency reference clocks that rely on both positive
and negative edges. In this case, it is desirable to maintain
as close to 50/50% as possible. If the duty cycle results
in narrow pulses, it will cause improper serial clocks from
the clock multipliers in the network switch PHY ports, thus
causing bit errors in the system.
Input/Output Levels: It is common to have
multiple voltage levels in the clock tree, depending on
the components used as well as the required input levels
to the interface components. The networking components are
continuing to operate at lower voltage levels with a view
to decrease the overall power consumption. Figure
3 shows an example of a network switch where a
crystal oscillator with 3.3V supply voltage provides the
reference clock for the network switch. The MAC circuit
interface requirement is 2.5V clock input. The PHY circuit
interface requirement is 1.8V clock input. In this example,
3.3V output from the reference clock crystal oscillator
feeds into the 2.5V clock buffer, as its output needs to
go to the MAC chip. Also, since the PHY chip needs 1.8V,
it needs to obtain the clock from either 3.3V crystal oscillator
or 2.5V clock output from the first clock buffer and then
feed into 1.8V interface of the PHY chip. We can assume
the following: 45/55% duty cycle from the 3.3V crystal oscillator;
1st stage clock buffer can accept 3.3V input and provide
2.5V output with 40/60% duty cycle; and the PHY port chips
need 40/60% duty cycle. Then, the second stage clock buffer
to the PHY chips must take in 40/60% duty cycle clock input
and provide 40/60% duty cycle clock output. So, the clock
buffers have to be able to handle higher input levels and,
at the same time, be able to provide duty cycle adjustments.
The output levels of the reference clock can be either single-ended
or differential, depending on the application. For systems
with stringent performance requirements like XAUI interface
for 10 Gigabit Ethernet, it is important to have reference
clocks that are differential so that common mode noises
are mitigated.
Output Rise/Fall Times: The output rise
and fall times need to be small because the clock cycle
time for high-frequency reference clocks is small. At the
same time, we need to ensure that excessive overshoot and
undershoot with fast edges doesn’t occur. For this
reason controlled slew rate is desirable.
Power Consumption: Increasingly, attention
is devoted to power efficient networking equipment and higher
performance PHY designs are developed for deep sub-micron
technology optimized for lower supply voltage. Therefore,
it is desirable that reference clock generators and clock
buffers operate at lower voltages down to 1V with the capacity
to operate with reduced power consumption. By having clock
buffers and interface components operate at reduced voltages,
we can eliminate the use of extra power rails and associated
regulator filter components.
Pericom’s offering of low voltage clock buffers
for networking applications:
Pericom recently introduced 1.2V-2.5V PI6C1080x/PI6CL1080x
clock buffers that can operate up to 250MHz for network
reference clock distribution applications. The clock buffers
have options to directly accept crystal interface for frequencies
up to 40MHz that eliminate the need for an additional crystal
oscillator. Figure 4 shows an example of
a timing solution for scalable Gigabit Ethernet switch where
Pericom provides both PI6C10806 clock generator/buffer to
distribute clocks for GE Switch PHY/MAC ports and provide
PI6C48535-11 differential clock generator/buffer to distribute
clocks for the switch fabric. Pericom additionally provides
matching crystals to go with both single-ended and differential
clock generator/buffers. Also available from Pericom is
the PI6C485352 twelve 2 to 1 clock mux to switch high frequency
reference clock for the XAUI interface to the switch fabric
backplane.
Pericom
Semiconductor Corporation
www.pericom.com
TXTLINX.COM 85
Email
this article to a friend!
|
