What It Takes to Make High Efficiency Ka-Band Amplifiers
By Damian McCann (CTO), Dr. Simon Mahon, Anna Dadello, Dr. Alex Bessemoulin, Dr. Jim Harvey, Peter Evans, Mimix Broadband, Inc.

In the modern world of military and commercial systems, ever increasing efficiency and power are being demanded. The reasons for this vary from basic thermal lifetime needs due to the reduced size of many components within which the PAs are being used, to total DC consumption as it relates to operational distances traveled by the object taking flight. High efficiency MMIC amplifiers can also offer overall system weight and mobility enhancements as compared to conventional waveguide, by combining techniques of smaller discrete amplifiers, eliminating the need for time consuming “chip and wire” tuning, as well as reducing sensitivity to shock and vibration. On-board bypass capacitors and reduction in MMIC sizing make them an ideal building block in larger power arrays such as GRID amplifiers, making it possible to produce an overall lower cost per watt of Ka-Band power when needed. The following work details some of the concepts and principles used by Mimix Broadband to create high efficiency Ka-Band MMIC amplifiers ultimately used in these systems. Since the key question is how to increase the overall efficiency, it is essential that we touch on some of the key efficiency trade-offs associated with the different elements in the overall design in order to recognize the best approach for the MMIC amplifier design.

Device Process Selection for MMIC Amplifier Cell
In addition to efficiency, the same MMICs used to reduce cost per watt must also be cost effective. The MMICs detailed in this article meet this challenge. A standard commercially available 6-inch GaAs pHEMT technology with 100-μm substrate was used in preference to thinner substrates [3]. This technology not only reduces cost, it also provides higher wafer robustness, easier die handling compared to thinner chips, and higher overall yield. The active MMICs use standard 0.15µm gate length pHEMT technology to maximize efficiency at Ka-Band. Reasonable die area and broad bandwidth were achieved with conventional technology by utilizing novel matching network topologies incorporating lumped elements, designed with extensive use of electromagnetic simulations.

MMIC Design – Optimal Cell Layout for Power Added Efficiency
Rigorous design and layout methods were used in the optimization of stability, gain, power transfer and lifetime. Layout parameters such as gate width, gate-to-gate spacing, and the number of gate fingers between source vias influence the RF power available from a transistor, its RF stability, the channel temperature (hence reliability and lifetime) and the size (cost) of the resulting amplifier. Load-pull measurements of test pHEMTs with on-wafer pre- and post-device matching quantify the effect of these layout parameters on the available RF power, which varies from 600 to 800 mW/mm, while keeping gate currents within a conservative range for reliable operation. In the design of any power amplifier, load- pull data is a necessary foundation. Using this methodology in our existing load-pull, we were also able to study the impact of cell layout on the optimal efficiency performance versus frequency.

Figure 1 shows how varying the gate width as the device is scaled can influence the available efficiency of the amplifier. This result is significant in that it shows the impact of manifold or device feed design, as it also influences the optimal frequency of use when developing load structures at Ka-Band, and consequently, the data that you compare. If reference planes and calibration standards are not well considered, it can also influence the final outcome of any such comparison.

Reproducing the Optimal Load-Pull Results – Optimum Matching Network Efficiency
Summary of Load-pull results taken at 6V on 600µm cells:

• Efficiency peaks at ≈ 57% at 36 GHz
• Optimal load impedance ranges from 12 to 40 ohms
• POUT ≈ +26 dBm

The design of the output stage transistor is a tradeoff between available RF power, thermal behavior, physical size and specified output match. Results of the load-pull and thermal imaging analysis are used for optimal design of the output stage and combining manifold. The use of lower power cells reduces the peak RF current required, thereby increasing the matching impedance presented to the power amplifier MMIC. The larger matching impedance, which is more easily realized, improves the repeatability and uniformity in manufacture of the matching solution. Larger impedance also reduces the matching circuit losses by lowering the transformation ratio to reach 50 ohms.

In MMIC design, resonant matching is the most straightforward means of impedance matching or transformation, and in most cases, the implementation is a multi-section cascade. The network may be low pass or high pass in nature, but the fundamental limitation to amplifier efficiency is the associated network loss. This loss is dependent on the “Q” of the individual matching element components and the impedance transformation ratio. The impedance transformation is related to the desired output power, the operating voltage, and most importantly, how this load impedance varies as a function of frequency.

To demonstrate this factor, we can formulate a strategy for optimal cell matching based on optimal network efficiency, understanding that required bandwidth and final output power will influence the overall result.

In Figure 2, we show how the network efficiency of the output power combined cells and impedance transformation can be optimized when using a resonant multi-stage transforming network. In this example, it is 3 stages. Fundamentally, the higher matching network losses associated with large impedance ratios lower network efficiencies and ultimately limit the power added efficiency of the amplifier.

Optimal network efficiency details how the peak load-pull performance of an optimal transistor design can be translated into optimal amplifier stage performance based on the impedance transformation required for that transistor cell, as well as the number of stages of impedance transformation required to combine the cell array at the reliable operating voltage being used for the amplifier.

Other key elements of the MMIC design include the following:

• Slot vias on each individual source terminal for minimum inductance and improved thermals
• Cell to cell biasing and bypass efficiency
• Compact matching networks by topology/design
• Through hole vias under MIM capacitors
• Spiral transmission lines
• High tolerance MIM capacitors

For the input and interstage designs, the load-pull data was augmented by a new non-linear device model [4] and extraction methodology [5] to ensure optimal trade off between power match for each stage and source impedance for the following stage. This new model and careful EM simulations ensure phase and amplitude balance between the amplifier’s inner and outer devices. RF ports and bias feeds were designed for ESD robustness.

Efficiency Techniques for MMIC Amplifier Design through Ka-Band
While not intending to review all efficiency enhancement techniques, at lower frequencies significant gains in efficiency have been obtained using harmonic terminations, most notably the use of Class F amplifiers. Literature [1] shows that a Class F amplifier can achieve a theoretical 100% drain efficiency by wave shaping the intrinsic drain voltage and current waveforms. When a device is biased at cut-off and driven into saturation, the voltage waveform is clipped and can be shaped like a square wave, and the current waveform can be shaped like a half sine wave with the proper harmonic terminations. The voltage and current waveforms do not overlap, thus minimizing the power dissipation. The square voltage waveform contains only odd harmonic frequencies. Ideally, all of these odd harmonic frequencies are terminated with an open circuit at the intrinsic drain of the transistor. The half sine wave current waveform only contains even harmonics, which need a short circuit termination for the harmonic current to flow.

It is not practical to terminate an infinite number of harmonics, but it has been demonstrated that with up to and including the 4th harmonic present and terminated correctly, the efficiency of an ideal amplifier can be as high as 86%.

The important thing, regardless of frequency, is shorting the 2nd harmonic and eliminating its presence as a voltage contributor. Doing this is not only beneficial in terms of efficiency, power and linearity, but as noted by Cripps et al [1], it creates the potential to realize additional power from the same supply voltage, if the termination is correctly phased.

Realistically though, the efficiency of the amplifier is limited by the transistors’ drain-source capacitance, Cds and its on state resistance, RON or knee voltage. Cds is often difficult to absorb into a multiple harmonic matching network. It also compromises the ability to terminate higher order harmonics. For this reason, a device with high FMAX when compared to the actual operating frequency is helpful in generating the higher order harmonics needed for wave shaping. In this respect, 0.15µm PHEMT is an excellent candidate for Class F amplifiers.

It should also be noted that these practical limitations restrict its use to relatively small amplifier output powers, as further cell combining severely limits its usefulness. It is, however, useful in amplifiers where power levels are consistent with the optimum cell design discussed earlier, and we have successfully used this approach in Ka-Band amplifiers up to almost 2W, as will be seen later.

In reviewing the Class F efficiency equations, it becomes clear that drain efficiency increases with larger load impedance, but at the expense of power. Therefore, VD should be set so that the peak voltage swing is equal to the breakdown voltage of the device. This achieves the highest output power for a given load impedance efficiency.

Figure 3 illustrates a Class F matching network. A quarter wavelength drain bias transmission line gives the lowest even harmonic impedances at the drain. Z2, θ2 and Z3 can be tuned to absorb Cds and simultaneously present a real load impedance at the fundamental and a very high impedance at the 3rd harmonic. It is possible with this network to terminate the 2nd, 3rd and 4th harmonics, as well as some of the higher order even harmonics.

Overall, selection of a sufficiently high intrinsic drain resistance provides the best compromise of drain efficiency and power output.

For example, a drain resistance of 70 ohms would result in a 3rd harmonic impedance of about 400 ohms. The 2nd harmonic impedance would be about 0.5 ohms, and the 4th harmonic about 0.7 ohms.

The nice thing about this network is that it is capable of tuning a fairly wide range of load impedances while maintaining a high 3rd harmonic impedance and realizable transmission line impedances in MMIC form.

Examples of Existing High Efficiency Ka-Band MMICs
The first set of MMICs is for applications around 35 GHz. Both 2 (Figure 4) and 3 stage (Figure 5) MMICs were designed.

At 35 GHz, a 2 stage 26 dBm single ended saturated design (2 stage amplifier with 13 dB gain) saw 38% PAE at 5.5V and 6V over a 6% bandwidth. At 10% bandwidth, the gain fell 1.5 dB with PAEs of 33% and 34% at 6V and 5.5V, respectively. All data was measured on block at room temperature. The 3 stage design was similar, with a reduction in PAE of approximately 10% when moving to a third stage.

At 30 GHz, a 2W single ended saturated design (3 stage amplifier with 22 dB gain) saw 35.8% PAE at 6V and 32.7% PAE at 5V over a 5% bandwidth. At 10% bandwidth, the gain fell 1 dB with PAEs of 28% and 26% at 6V and 5V, respectively. All data was measured on block at room temperature. These are outstanding results and are shown in Figure 7.

A combined version of the MMIC yielded PAE of 31% and almost 4W of power output at 30 GHz and is shown in Figure 8.

At 35 GHz, Figure 9 shows 3.6W single ended saturated design (3 stage amplifier with 22 dB gain shown in Figure 6), which saw 26% PAE at 6V over an 8% bandwidth.

Conclusion
Mimix Broadband’s state-of-the-art MMIC development methodology uses load-pull and thermal measurement techniques to characterize active device properties and performance. This data enables accurate models and validates all RF simulations. Wafer probed s-parameter measurements verify models and simulations of all passive structures. This methodology results in a detailed technical comprehension of the PAM operation and performance, which results in shorter development time and ultimately yields increased efficiency.

A summary of some of the MMICs designed for highest efficiency are presented in Table 2.

Acknowledgement
The authors would like to acknowledge the contributions of Kevin Cen, M.G. McCulloch, R.G. Mould and S. Hwang for assistance with measurements and assembly; A.E. Parker (Macquarie University) and P.V. Vun for associated non-linear modeling supported by the Australian Research Council. The authors would also like to acknowledge the valuable input given by David Richardson, Vincent Pelliccia and Jeff Kovitz.

References
[1] S.C. Cripps, RF Power Amplifiers for Wireless Applications, 2nd ed. Norwood, MA: Artech House.
[2] S. Mahon, A. Dadello, J. Harvey, and A. Bessemoulin, “A family of 1, 2 and 4-watt power amplifier MMICs for cost effective VSAT ground terminals,” 2005 IEEE CSIC Symposium, November 2005.
[3] M. Chertouk, D. W. Tu, P. Meng, C. G. Yuan, W. D. Chang, C. Y. Kuo, C. C. Chang, A. Chang, H. H. Chen, C. H. Chen, and P. C. Chao, “Manufacturable 0.15μm PHEMT process for high volume and low cost on 6” GaAs substrates: The first 0.15μm PHEMT 6” GaAs foundry fab,” 2002 GaAs MANTECH Conference.
[4] J. Brinkhoff, A. E. Parker, S. J. Mahon, and G. McCulloch, “Symmetric HEMT drain current model for intermodulation distortion prediction,” Proc. Workshop on the Applications of Radio Science 2006, ISBN: 0- 9580476-0-X, pp. 1-9, Leura, NSW, Australia, February 2006.
[5] A. E Parker, and S. J. Mahon, “Robust extraction of access elements for broadband small-signal FET models,” 2007 IEEE Int. Microwave Symp. Dig., pp. 783-786, June 2007.

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