Understanding Gate Lag and How it Differs From Switching Speed
By Andrew Freeston, Principal Engineer, Design and Applications, Tyco Electronics Wireless Systems Segment, M/A-COM

In today’s world of rapidly changing technology, systems are being designed with speed in mind. From sensors to processors, every designer wants to avoid delay of all kinds. To maintain very high bandwidth and linearity performance, many engineers choose Gallium Arsenide pHEMT switch products for their designs. With the increasing pressure for systems to do things faster, device lag times have become critical parameters. To meet this need, Tyco Electronics’ M/A-COM has developed a technology to ensure rapid settling.

Traditionally, the time it takes for the switch to change state has been referred to as switching speed. Switching speed is defined in several ways. Typically, it is a measurement which characterizes the amount of time elapsed between a change in control and the point that the measured parameter has reached 90% of its steady-state value. The remaining 10% is typically a logarithmic change, and can take a relatively long time to reach the steady-state point. For most systems, this has been adequate; the receiver is getting ample signal, the mixer output is getting to the right place, the diversity switch changes antennas successfully. However, recent applications are demonstrating a clear need for the device to be 100% settled in a much shorter time.

State of the art test instruments, high power / high bandwidth transmitter chains, radars and systems with large matrices of cascaded switches are very sensitive to that last 10% of the change. That last 10% is called Gate Lag. Tyco Electronics’ M/A-COM has developed a proprietary pHEMT semiconductor fabrication process that is highly optimized for excellent gate lag performance.

Gate lag is most commonly specified by giving the final settled on-resistance of an insertion path and the resistance in ohms-variation between two times after the device is switched. It can also be quantified in terms of settled RF envelope, but this is more difficult to measure in a production environment. The measurement of resistance variation directly correlates to the settling of RF envelope and can be used as a screening parameter in a production test environment.

Conventional switching speed is the relative change in state from 10%-90% of the steady-state RF envelope. See Figure 1 for a graphical explanation of these concepts.

In Figure 1, the units are irrelevant for the discussion at hand. The time elapsed from the point at which the control signal (blue) is at its 50% point until the RF Envelope (red) is at its 90% point is traditionally called Ton. The time that elapses from the point where the RF Envelope has changed 10% from its prior state until 90% of its final state is called Trise. Toff and Tfall are simply the expressions used for the opposite change. Toff is the time it takes from the 50% change in control logic to the point at which the parameter has gone 90% of the way to the “off” state. Tfall is the time it takes from the point the parameter has gone 10% of the way toward the “off” state until it gets to the 90% “off” point.

Gate lag is a measurement which begins at some point after the 90% point, and continues to the final settled value (or other arbitrarily defined point). If the “RF Envelope” trace in Figure 1 was actually a measurement of DC path resistance, in ohms, the gate lag from 90% to 100% changed would be 0.1 ohms. This delta resistance is measured over the period of time it took to be considered finally settled or to some arbitrarily longer time. Gate lag is usually looked at in terms of resistance change over milliseconds after the control signal is changed. Switching speed is typically measured in nano or micro seconds after the control signal is changed.

The primary cause of switching delay is simply related to the time decay effect of changing a static charge. Let’s consider switching a depletion-mode GaAs PHEMT device as biased in a typical RF switch. The circuit shown in Figure 2 depicts a single PHEMT FET device, with a pulsed gate voltage and a constant drain voltage. This circuit includes a 50 Ohm current limiting resistor, which is used in a typical measurement. Using Ohm’s Law, we can measure the voltage drop across that resistor. We know the resistor value, therefore we can calculate the on resistance of the switch path which is switching from ground to nearly open as the gate voltage is pulsed.

Figure 3 shows the simulated gate lag in ohms for the setup in Figure 2. The markers show the change in on-resistance over a certain time period.

For Figure 3 it would be said that it has a gate lag of 0.57 ohms from 66nS to 290nS, although it can be seen that the change after 140nS is negligible.

Several things cause the lag to be present, and we can describe them in terms of resistance and capacitance. Consider that the gate of a FET is somewhat lossy, and clearly very small. Then consider that a certain potential is applied across it and a particular source. Next, recall that in most switch designs a large valued gate resistor is present for DC-RF isolation. When the device gate control voltage is changed, there will be an RC time constant limiting the state transition. (This is a first order approximation; the device channels need to be depleted or restored, the field around the gate needs to be created or removed, etc.).

Tyco Electronics’ M/A-COM’s process optimized for low gate lag results in a dramatic improvement over the standard pHEMT device. Devices run on this process are optimized in a manner that allows for a more rapid change of the charged regions of the device, giving the switching transition a sharper, more desirable shape.

Figure 4 shows the on resistance (measured) on the MASWSS0192 switch vs. time. The MASWSS0192 is manufactured on the improved process.

The same switch manufactured on a standard GaAs pHEMT process is shown in Figure 5.

As can be seen, the on resistance performance and variation are dramatically improved. It is also notable that the wafer-wafer switching characteristics are much more consistent on the improved process.

It is important to consider that in the isolated or “off”, condition the device has thousands of ohms of resistance. A device could meet the 90% settled point rapidly, yet still have a long way to go to be settled; the absolute range of change is very large. On high isolation switches, the standard switching speed specifications can be misleading, since the transition is proportional to the absolute signal level variation. The sharper turn-on characteristics of the low gate lag process provide dependable rapid transitions.

Figures 6-8 show measured data taken on the MASWSS0093 and the MASW-007588. The MASW-007588 is the low gate lag version of the MASWSS0093. Figures 6 and 7 have the same scale; Figure 8 is “zoomed in” along the time scale, to allow for a better measurement. Each of these gives information important for evaluating the long term settling of an RF Envelope.

The three measurements shown in Figures 6-8 display envelope and control waveforms vs. time. The red lines are the control signals, and the green is the RF Envelope measurement.
Now would be an appropriate time to discuss the measurement technique used to acquire this data. We start with a standard sample board with a given switch device. Then the DC blocking capacitors and DC control capacitors are removed. A function generator with complementary outputs of 0/-5V is set up. The function generator period must be sufficiently long enough to allow for the device to settle completely. It is important to try longer periods to ensure that the device under test is fully settled.

Cables must be short and neat to reduce transient ringing in the system. Any slowness or ripple in the function generator pulses will reduce the accuracy of the measurement. The small amount of ripple on the pulses in Figure 8 does have a small effect. This was the generator that was available for the testing and clearly demonstrates the improvement of our optimized process.

The DC gate lag measurement can be made by setting the oscilloscope to trigger on one of the control lines. Short one path of the switch, leaving the other open, and measure the common port with the oscilloscope in high impedance mode. To that same common point connect a measured resistor of about 50 ohms, and apply 1V to it.

Now connect the function generator outputs to the control lines of the switch. Once this is set up you should see a voltage rising and falling as the switch connects its common port to the shorted port.

In Figure 9, the oscilloscope measurement will give a voltage drop across the current-sense resistor.

Knowing the input voltage, and the voltage drop, and the resistance, the resistance of the DUT (Ron) can be calculated using Ohm’s Law.

Consider that the voltage at the oscilloscope is called V2, and the voltage at the supply is called V1. The current through the known value resistor is determined by:

where R_Value is the fixed known resistance of the current sensing resistor.
Knowing the current and the value of V2, we can simply calculate the on resistance of the DUT using the following formula:

For measuring the RF Envelope versus time, the setup is slightly different. The oscilloscope port at the DUT should be set to 50 ohms, and an isolator is needed.

The isolator is needed because often times the oscilloscope port return loss is not very good, and this mismatch will cause the data to be inaccurate. The RF Envelope mode should be enabled in the oscilloscope and the power on the signal generator applied.

In addition, be sure the signal generator is generating a low enough frequency to be observed on the oscilloscope.

It is important to remember that one needs to be careful not to apply too high a DC voltage to the DUT; it should be no more than 1V at the resistor. Figure 10 has been added to illustrate the measurement setup for Envelope-based settling time measurements.

Let us consider a practical example. Suppose we have a switch that has 1dB insertion loss and 30dB isolation at a particular frequency. From that, we can predict what the insertion loss would be at 90% and 10% of its change. See the following algebra:

Since our decibel notation is based on a logarithmic comparison, it may be surprising to see the 10% and 90% points in terms of settled decibel loss.
If we consider a 50 ohm system, and a device with 1dB settled insertion loss and 30dB isolation, we can calculate the “on” and “off” DC resistance as follows:

Using the above formulae, one can deduce that the DC “on” resistance for this device at 90% is 18.3 ohms, leaving about 6 ohms to settle over the final 10 percent. Tyco Electronics’ M/A-COM’s new low gate lag products dramatically adjust the rate of change during that final 10 percent to meet the needs of timing-sensitive designs. (Refer back to Figures 6 and 8 to see the 2000x improvement.)

If we want to convert Rdevice to insertion loss in dB, we have the following formula:

With this, we can determine to a first order approximation the insertion loss at a given point along the on resistance curve. It is an approximation because the on resistance is a purely DC measurement, where in the RF environment the FET devices have some fixed drain-source capacitance (Cds). This Cds would only help to improve the settling speed in this case, so this model is considered to be conservative.

In summary, a method has been shown for measuring the parameter gate lag. Gate lag has proven to be a highly important parameter in test systems, packet-based data transmissions, radar systems and many other applications that are time-variation critical. Tyco Electronics’ M/A-COM has developed a semiconductor fabrication process to address these industry needs. The current portfolio of low gate lag products includes:

In response to large demand, this portfolio is expanding rapidly. Contact Tyco Electronics’ M/A-COM to find out about the latest low gate lag products. If you have questions on this topic, or others, please contact Tyco Electronics’ M/A-COM’s Applications Team.

Tyco Electronics’ M/A-COM

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