Fabrication and Electrical Performance of Z-Axis Interconnections: An Application of Nano-Micro-Filled Conducting Adhesives
By Voya R. Markovich, Rabindra N. Das, Michael Rowlands and John Lauffer, Endicott Interconnect Technologies, Inc.

The Need for Increased Density
The needs of the semiconductor marketplace continue to drive density into semiconductor packages. The high end of this market appears to be standard Application-Specific Integrated Circuits (ASICs), structured ASICs, and Field-Programmable Gate Arrays (FPGAs). These devices continue to need increasing signal, power, and ground die pads, and a corresponding decrease in pad pitch is required to maintain reasonable die sizes. The combination of these two needs is driving more complex semiconductor packaging designs. Traditionally, greater wiring densities have been achieved by reducing the dimensions of vias, lines, and spaces, increasing the number of wiring layers, and utilizing blind and buried vias. However, each of these approaches possess inherent limitations, such as those related to drilling and plating of high aspect ratio vias, the reduced conductance of narrow circuit lines, and the increased cost of fabrication related to additional wiring layers.

One method of extending wiring density beyond the limits imposed by these approaches is metal-to-metal z-axis interconnection of sub-composites during lamination to form a composite structure. Conductive joints can be formed during lamination using an electrically conductive adhesive. As a result, it is possible to fabricate structures with vertically terminated vias of arbitrary depth. Replacement of conventional plated-through-holes (PTHs) with vertically terminated vias opens up additional wiring channels on layers above and below the terminated vias and eliminates via stubs, which cause reflective signal loss.

Conductive Adhesives
During the past few years, there has been increasing interest in using epoxy-based electrically conductive adhesives as interconnecting materials in the electronics industry. Conductive adhesives are composites of polymer resin and conductive fillers. Metal-to-metal bonding between conductive fillers provides electrical conductivity, whereas a polymer resin provides better processability and mechanical robustness. Conductive adhesives usually have excess filler loading that weaken the overall mechanical strength. Therefore, the reliability of the conductive joint formed between the conductive adhesive and the metal surface to which it is mated is of prime importance. Conductive adhesives can have broad particle size distributions. Larger particles can be a problem when filling smaller holes (diameters of 60 µm or less, e.g.), resulting in voids.

In this study, adhesives formulated using controlled-size particles ranging from nanometer scale to micrometer scale were used to fill small holes having diameters ranging from 50 µm to 250 µm for Z-interconnect applications. For example, holes 50-75 µm in diameter are suitable for chip carrier interconnects, whereas 100-250 µm diameter holes are suitable for board-level interconnects.

A variety of metals, including Cu, Ag and LMP (Low Melting Point) alloys have been used to make the conductive adhesive. Nanoparticles of silver were chosen because of their higher electrical conductivity and chemical stability. Nanoparticles were mixed with microparticles to improve the sintering behavior of the adhesives. Addition of a conducting polymer was found to increase the overall mechanical strength without compromising electrical conductivity. LMP and LMP-coated particles melt during processing and produce a continuous metallic network. The adhesive was applied onto Cu substrates by printing or coating.

The study was extended to the development of a Z-axis interconnect construction for a laminate chip carrier and printed wiring board (PWB). This structure employs an electrically conductive medium to interconnect thin cores (subcomposites). The cores are processed in parallel, aligned, and laminated to form a composite. The net effect is a composite laminate having vertical interconnections with small/large diameter holes that can terminate arbitrarily at any layer within the cross section of the package. There is no requirement for PTHs to be formed at the composite level. This effort is an integrated approach on three fronts: materials development and characterization, fabrication, and design and electrical characterization at the board level.

Experimental Procedure
A variety of silver, copper, and LMP-based nano and micro particles and their dispersion into epoxy resin were investigated in order to achieve uniform mixing in the adhesive. In a typical procedure, epoxy-based conductive adhesives were prepared by mixing appropriate amounts of the conducting filler powders and epoxy resin in an organic solvent. For conductivity measurements, a thin film of this paste was deposited on a substrate and cured at different temperatures ranging from 150ºC to 265ºC. For reliability assessments, two paste films were laminated together.

For fabrication of a high-density laminate chip carrier, a 0S/1P joining core structure was constructed using a 35 µm-thick copper power plane sandwiched between layers of a dielectric material composed of silica-filled allylated polyphenylene ether (APPE) polymer. Through holes in the joining cores that were formed by laser or mechanical drilling, with diameters ranging from 50 µm to 250 µm, were filled with an electrically optimized conductive adhesive. The adhesive-filled joining cores were then cured and cross-sectioned to evaluate hole fill quality.
Adhesives were characterized by SEM and optical microscopy to ascertain particle dispersion and interconnection mechanism. A Keithley micro-ohmmeter was used for electrical characterization. Viscosity at room temperature (25ºC) was measured, and the heat of the reaction of the adhesives was studied using a differential scanning calorimeter (DSC). Practical adhesion (90 degree peel test) and tensile strength were measured using an Instron (Model 1122) and MTS tensile tester, respectively.

Results and Discussion - Nano-Micro Filled Conductive Adhesives
Nanoparticle generally refers to the class of ultra fine metal particles with a physical structure or crystalline form that measures less than 100 nm in size. They can be 3D (block), 2D (plate), or 1D (tube or wire) structures. In general, nanoparticle-filled conductive adhesives are defined as containing at least some percentage of nanostructures (1D, 2D, and/or 3D) that enhance the overall electrical conductivity or sintering behavior of the adhesives. It is well known that change in grain size has a direct impact on the electronic properties of a system. In view of this, a systematic investigation of the electrical resistance behavior of silver nano and nano-microcomposites was carried out, and the results of such investigation are presented here. Sintering temperature can be greatly reduced when the size of particles is decreased to 5-15 nanometers. Due to the decrease of size, diffusion and growth of the nanoparticles is much easier, and large grains (hundreds/thousands of nanometers) can be efficiently produced. These nanoparticles diffuse with each other and are gradually sintered by neck-formation between the adjacent particles during the thermal anneal process on the substrate. The neck can be smoothed away gradually. The grains of nanoparticles convert into a continuous surface.

A variety of nanoparticles ranging from 10 nm to 80 nm were used to modify micro adhesive composites. (Particle size has a direct impact on particle diffusion/sintering.) SEM images indicate that sintering of a system containing 10-15 nm particles starts at 200°C (nanoparticles were sintered, some microparticles remained unsintered) and completes at 240°C (all particles sintered). For comparison, 80 nm particles have been shown to sinter around 275°C. In the nano-micro composites, the main components are a mixture of nanoparticles and microparticles. The nanoparticles may contact with the adjacent ones, but the nano aggregation lengths are short, less than 10-fold of the microparticle diameter, on average. As the sintering temperature increases, particle diffusion becomes more and more obvious. The aggregation length becomes much longer, resulting in the formation of one-dimensional jointed particle assemblies developing into a smooth continuous network.

The addition of nanoparticles reduced sintering temperature without compromising electrical conductivity. Figure 1 shows nano-micro composites sintered within micro-via. The observation suggests that the sintering mechanisms are the same for the nano-micro composites where micro particles play an important role and the excess amount of microparticles will prevent low temperature diffusion/sintering.

A variety of conducting polymers, blended with appropriate polymers and cured at ~190ºC for 2 hours, showed low volume resistivity in the range of 10¯5 ohm-cm, which is similar to that of micro-filled adhesives. Volume resistivity decreased with increasing curing temperature due to sintering of metal particles. Adhesion between the adhesive and the substrate to which it is mated is critical to the reliability of the semiconductor package. Bond strength of conducting-polymer-modified adhesive joints was evaluated using tensile strength measurements. Micro-filled adhesives showed high tensile strength when laminated with Gould JTC-type Cu foils and showed cohesive failure. Conducting polymer doped samples did not show any failure. Here, adhesive (glue) used to attach laminates to test fixtures ruptured prior to the test structures. This indicates that conducting polymer modified samples result in highly conductive adhesives with good mechanical strength. Conducting-polymer-based LMP samples showed high mechanical strength. Typically, LMP-based samples show mechanical strength in the range of 600 PSI. Addition of conducting polymer enhances the mechanical strength to 1800-2000 PSI. Figure 2 shows the tensile strength measurements of conductive adhesives. Conducting polymer silver-filled paste yielded the maximum mechanical strength.

Conducting adhesives cured at 200ºC for 2 hours showed low volume resistivity. All silver nano-micro composites showed a resistivity of about 10-4 to 10-6 ohm-cm. Resistance decreases with increasing curing temperature due to sintering of metal particles. Figure 3 shows change of volume resistivity of nano-micro silver paste as a function of curing temperature. There is a significant resistance drop with increasing curing temperature from 150ºC to 200ºC for nano (80 nm) and nano-micro particles. Change in resistivity with a nano-micro system was significant when cured at 200ºC and 275ºC (+10). Resistivity data indicate that although nano or nano-micro paste sintering starts at a lower temperature (100-150 ºC for nano and 200ºC for nano-micro), it requires complete sintering to achieve the lowest resistive joints.

Core Fabrication
A few optimized metal-epoxy adhesives were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECAs. Z-axis interconnection was achieved using joining cores, that is, cores with no signal planes, but incorporating a thermoplastic, or uncured, thermoset dielectric material for purposes of dielectric to dielectric joining, and ECA-filled vias for purposes of metal-to-metal joining with adjacent signal cores. Around 5,000 to 200,000 through- holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 µm to 250 µm, were filled with an optimized ECA. The adhesive-filled joining cores were laminated with circuitized subcomposites to produce a composite structure. High temperature/pressure lamination was used to cure the adhesive in the composite and provide Z-interconnection among the circuitized subcomposites. A variety of joining core and subcomposite structures such as 0S/1P, 0S/2P, 2S/1P, and 2S/2P were used for hole fill applications The cores can be structured to contain a variety of arrangements of signal, voltage, and ground planes. In addition, signal, voltage, and ground features can reside on the same plane. Figure 4 shows optical photographs of a joining core (0S/1P) having paste-filled holes.

Full-Z Board Fabrication/ Case Study:
Integral to the methodology described in this article is the use of core building blocks that can be laminated in such a manner that electrical interconnection between adjacent cores is achieved. As a case study, this micro array based Z-interconnection methodology was used to fabricate a package for a board device having a pad pitch of 375 µm. Two basic building blocks are used for this case study (Figure 5). One is a 2S/1P core. The power plane (P), a 35 µm thick copper foil, is sandwiched between two layers of a dielectric. The dielectric is used because of its favorable electrical, mechanical, and thermal properties. The dielectric constant and loss tangent of the dielectric at 10 GHz are 3.0 and 0.0038, respectively.

The signal (S) layers are comprised of copper features generated using a subtractive process. A line thickness of 35 µm was achieved with minimum dimensions for line width and a space of 75 µm each. Minimum land-to-line spacing was also 75 µm. Mechanically drilled-through vias had a diameter of 200 µm. The diameter of plated pads around the through vias was 300 µm.

The second building block is a 0S/1P core, or joining core. This core is constructed using a copper power plane, 35 µm thick, sandwiched between layers of a dielectric material. Through holes in the core are filled with an electrically conductive adhesive. A 23-metal-layer structure with twelve signal layers composed of eleven subcomposites (six 2S/1P cores and five 0S/2P cores) is shown in Figure 5. The adhesive-filled joining cores were laminated with circuitized subcomposites to produce a composite structure. Proper preparation of the subcomposites is crucial to obtaining robust, reliable micro array joining between dielectric layers and between the conductive paste and the opposing copper pad. Sufficient flow of the dielectric materials must be achieved during lamination to allow for complete encapsulation of circuitized features and good dielectric-to-dielectric bonding.

Electrical Performances:
Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies (Figure 6). The measured insertion loss for narrow, short lines and wide, long lines is similar. The Z-interconnect stackup and low dielectric constant, organic dielectric allowed wide, 50-ohm, lines. The Z-interconnect paste has little effect on the signal, except to add a small via length to it. The performance is similar to a solid copper barrel. The Z-interconnect paste does not degrade the signal significantly. We also ran some simulations to generate eye diagrams using raw data measured from the full-Z TV. We considered eye diagram simulation using measured Sparameters from 6 inch length net for four Z-interconnect joints and compared it with no Z-interconnect joints. It is clear from eye diagram simulation that Z-interconnect does not degrade 10Gbps data.

Conclusions
A variety of nano and micro filled Cu, silver and LMP-based conducting adhesives were used for a Z-axis interconnection application. High aspect ratio, small diameter holes anywhere in the range of 50 to 300 microns were successfully filled. Addition of nanoparticles reduced sintering temperatures of microfilled conducting adhesives. Conducting-polymer-based adhesives were mechanically better than micro- and LMP-filled adhesives. All adhesives maintained high electrical conductivity and tensile strengths. The adhesive-filled joining cores were laminated with circuitized subcomposites to produce a composite structure. High temperature/pressure lamination was used to cure the adhesive in the composite and provide stable, reliable Z-interconnections among the circuitized subcomposites.

A full-Z interconnect with sub-composites and joining layers can successfully be built. The conductive paste showed good signal transmission to 25GHz. Z-interconnect construction allows wide (7.4 mils) and narrow (3.6 mils) lines in the same stack-up. Wide lines (7.4 mils) in organic full Z-interconnect boards have signal loss less than 0.6 dB/inch at 10GHz, and less than 1.0 dB/inch at 16GHz. A full-Z taconic board can carry 25Gbps for at least 12”. Very low-loss multi-GHz, controlled-impedance transmission lines can be built using Z-interconnect with organic dielectric materials. Z-interconnect can be used in single and multi-chip applications. By designing an organic package without electrical stubs and without through holes, high wiring density and excellent electrical performance can be achieved. This novel method of providing vertical electrical interconnections in organic substrates can help semiconductor packaging keep pace with the needs of the semiconductor marketplace.

Endicott Interconnect Technologies, Inc.
www.eitny.com
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