Single SONET VCO Can Replace Multiple SAW VCOs
by Ramon Cerda, Vice President of Engineering, Crystek Corporation

Engineers of broadband networks still regularly use SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) rings, and this demand keeps new generations of equipment constantly under development. Inside the equipment, there exists at least one frequency source at the Optical Carrier level being used, such as OC-12. In many cases, these frequency sources are implemented around a VCSO (voltage controlled SAW oscillator) and PLL (phase-locked loop) circuitry. There’s more than just one frequency or function (frequency translation, frequency de-jittering) that must be performed, thereby requiring multiple VCSOs. There are also the Forward Error Correction (FEC) frequencies that may need to be generated or accepted (see Table 1).

Hence, reducing price by reducing the number of VCSOs while at the same keeping all the frequency options would be ideal. But the main problem with SAW-based oscillators is that only one frequency can be generated per SAW resonator. There are some oscillators that switch the SAW resonators to generate two or more frequencies, but price can be prohibitive with these components. Adding on many SAW-based oscillators is not cost effective, and the best solution is to employ one low-cost oscillator that generates many rates but still complies with all requirements.

The Solution
It is now possible for a newly designed VCO with LVPECL outputs to replace several VCSOs for SONET/SDH OC-12 rated applications. In designing in one of these new VCOs, one must give careful consideration to the phase locked loop dynamic performance in order to comply with the jitter transfer requirement as specified by Telcordia GR-253-CORE.

SONET/SDH equipment must comply with a jitter generation and jitter transfer as described in Telcordia GR-253-CORE, American National Standards Institute’s (ANSI) T1.101-1999 and International Telecommunications Union’s (ITU) T G.813. SAW-based VCOs have been used for many years for SONET/SDH due to their low phase noise, low jitter performance.
Jitter generation can be directly correlated to the phase noise performance of the VCO and its PLL circuitry. Therefore, any proposed VCO replacement must have a certain phase noise performance in order to comply with GR-253-CORE.

One viable VCO solution is Crystek’s model CVCO57P-0610-0700 (Figure 1) which spans from 610MHz to 700MHz. This tuning bandwidth will cover all frequencies listed in Table 1. The CVCO57P-0610-0700 is also packaged in a 5mm x 7.5mm with LVPECL logic outputs that will fit in the same footprint as standard VCSOs. Being in the same package and same output logic means that engineers can more easily integrate the new VCO design into their equipment without PCP layout changes.

Phase Noise Performance
The phase noise performance of a typical VCSO, along with that of the proposed VCO, is shown in Figure 2. It turns out that the phase noise floor of about -145dBc/Hz is limited by the LVPECL driver. The close-in phase noise, on the other hand, is proportional to the loaded Q of the oscillator. For SONET, phase jitter is calculated by integrating the phase noise plot over a specific band of interest, such as 12KHz to 20MHz, or 50KHz to 80MHz. In order to meet the jitter generation of SONET, the phase jitter must be less than 1pS RMS over 12KHz to 20MHz or 50KHz to 80MHz bands.

Calculating the RMS phase jitter from 12KHz to 20MHz for both plots in Figure 2 gives us 0.21pS for the CVCO57P-0610-0700 and 0.23pS for the CVCSO at 622.08MHz. Both are well within the required specification of 1pS RMS of phase jitter maximum.

Guidance in Designing the PLL
Designing a PLL to meet SONET jitter transfer requirements is very different than designing a PLL for radio applications. The first letter in SONET is for “Synchronous,” which means all the pieces of equipment are locked together. Each component in the ring locks to the incoming signal and passes it along to the next equipment. If each PLL starts to add too much jitter, it will accumulate to a significant level. The jitter will grow so much that, eventually, equipment down the ring will not be able to recover the clock, and the ring will stop working.

PLLs for SONET are designed to be “sluggish” so as not to transfer jitter (no jitter peaking). This means designing the PLL with a damping factor of 6 or greater. This is in sharp contrast to PLL designs for radio applications, where a damping factor of 0.7 is often chosen.

The tuning sensitivity (Kv) of a VCSO and the CVCO57P-0601-0700 are very different. The Kv for a typical VCSO is about 0.2 MHz/V, while the CVCO57P offers tuning sensitivity of about 30 MHz/V – the difference between a low gain loop and high gain loop. With 30MHz/V, one can easily design the loop without an active filter, which not only saves component count, but also removes another potential source of noise and/or jitter.

In order to have a low-jitter PLL design, the power source to it must be very “clean.” Any switching noise will contribute to deterministic jitter. As such, a separate low noise voltage regulator is strongly recommended for the VCO and PLL circuitry.

Crystek Corporation
www.crystek.com
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