Design Considerations for a 28G Bit Error Ratio Receiver
by D. Jain, Inphi Corporation

Increasing consumer demand for high bandwidth applications for sharing video and images, as well as the new paradigm of cloud computing, are driving the development of new optical communications standards like 100 Gigabit Ethernet (100 GbE) and 40 Gigabit Ethernet. In the server space, storage and I/O virtualization have resulted in increasingly data-intensive and high-speed networking applications. Data centers are demanding high bandwidth interconnects between these systems and their input/output devices. As a result, next-generation standards for 14G Fibre Channel & Eight X Data Rate (EDR) Infiniband are being commercialized to scale the capacity of Storage Area Networks (SAN).

These systems have individual components and subsystems that need to work at high-speed serial rates well above 12.5 Gbps. For instance, a 100 GbE transmitter and receiver system is shown in Figure 1.

The optical signal incident on the photodiode suffers severe dispersion due to non-linearities in the fiber. The TIA needs to regenerate the data pattern with better than 10-12 bit error ratio (BER) with worst case fiber and data patterns up to 28 Gbps. Similar BER testing needs to be done for 100G DP-QPSK (4x28 Gbps), 40G DQPSK (2x22 Gbps), 14G Fibre Channel (1x14 Gbps) and Infiniband EDR (20 Gbps serial rate). While R&D is underway to develop such ICs and systems for these standards, there remains a void for testing of these components and systems above 12.5 Gbps. Currently, R&D labs have limited options for testing prototypes. Typically, they first consider buying high-speed Bit Error Ratio Testers (BERTs) which can measure the BER and create bathtub curves, BER versus OSNR curves, etc. However, above 12.5 Gbps, the cost of these BERTs can be prohibitive. Hence, many companies would like to put together in-house solutions using components from high-speed semiconductor vendors, greatly reducing the capital investment. The simplest and most cost effective solution involves de-multiplexing the serial data down to a low enough rate where existing 10G BERTs can be used. However, with speeds going up to 30 Gbps, building these de-multiplexer solutions becomes increasingly challenging. The most important challenges lie in the inherent microwave nature of the board, the use of suitable high frequency connectors, and the transition design from board to connector. Unfortunately, these challenges prevent most companies from building these solutions.

To fill the void between high-end BERTs and low-cost in-house solutions, reference designs are now available to greatly simplify such systems by integrating most of the required high-speed components. One example is the 28821BR 28 Gbps BER Receiver Evaluation Board from Inphi Corporation (Figure 2). In this article, we will review some of the high-speed design challenges, approaches, and results from this board.

The 28821BR puts together multiple Inphi high-speed ICs working up to 30 Gbps. At the heart of the system is the 5081DX, a 1:4 de-multiplexer in a GPPO connector metal package designed to work up to 50 Gbps. The clock and data front ends consist of 25717CF Clock Fan-Out ICs, providing high input sensitivity. The three 20709SE selectors allow the user to select any one of the four low speed outputs. PRBS data patterns have a special property that, on down-conversion by an integral power of 2, each of the resultant low speed data streams is an identical PRBS pattern (with various phase offsets). Thus, if the component needs to be tested with a 28 Gbps PRBS31 pattern, the de-multiplexed output of the 28821BR will also be a (shifted) PRBS31 pattern at 7 Gbps, allowing easy recognition by Error Detectors on legacy 10G BERTs.

Figure 3 shows a typical usage model for the 28821BR testing a Device Under Test (DUT). A copy of the high-speed serial input data stream is output and can be sent to a Clock Recovery Unit. A DC Switch Matrix is connected via the Output Selection Control port to control the two Select Bits; these two bits switch between the four possible de-multiplexed data streams to be output to the 10G BERT. The BERT compares the captured data with a known pattern (e.g. PRBS), and the results can be uploaded to the PC via the LAN connection.

The key features for this board include:
1. Very high input sensitivity of 100 mV single-ended on the data port and 200 mV
single-ended on the clock port

2. The low speed data output stream can be electrically selected (one of four) to enable automated testing of the complete high-speed data stream by switching between the four channels

3. Any random, non-PRBS pattern can be tested by appropriately programming the expected pattern on the BERT. Often, testing involves using custom pattern, e.g. long strings of 0 are followed by a lone 1 (or vice versa)

4. Clock phase margin in excess of 200 degrees at 28 Gbps to enable BER testing of severely distorted input eyes

5. Low jitter, high swing output clock and data at the de-multiplexed rates for easy connection to 10G BERT systems

6. Buffered versions of the input high-speed clock and data provided back to the user

Design Challenges
The design of this board entailed several challenges that arose only at these microwave frequencies.

1. Board Material: To balance cost, mechanical strength, and electrical performance, the board stack-up consists of five layers of low cost FR4 with the top layer made of low loss Rogers 3003. Power, GND and low frequency signals are routed on the lossy FR4 material (tan d = 0.025), while all the high-speed traces are routed on the top layer. Low dielectric constant (er=3.0 @ 10 GHz) and low losses (tan d = 0.0013 @ 10 GHz) allow preserving sharp edges of the digital signal as it travels along the transmission line.

Transmission Line Design: All high-speed signals on the top layer are laid out as ground backed coplanar waveguide (GB-CPW) with 50 ohm impedance. Shielding ground adjacent to the traces on the top layer is shorted with vias to the GND reference plane on layer 2 to avoid unwanted parallel plate waveguide modes.

DMUX to Board Interface: Perhaps the most challenging part of this design is the DMUX to board interface. The 5081DX 1:4 DMUX is housed in a metal package with GPPO connectors. Since it has 14 I/Os, using cables with edge-launch connectors to interface to the board consumes too much area and significantly drives up the cost. Instead, we used the surface mount high-speed connector (82-MMPX) from Huber-Suhner.

The transition from the connector to the board needs careful design using a full-wave 3D electromagnetic simulator. A 3D model for the connector, including the transition to the substrate, has been simulated to ensure good performance and manufacturability. Figure 4 shows the 3D model used and Figure 5 shows S-Parameters of the transition. The results show that the transition has been well optimized to give excellent performance.

The simulations were compared to measurements to validate the design process using special test coupons as well as the actual connectors on the 28821BR board. Measured results in Figure 6 show the return loss for the connector to board interface to be better than -24 dB up to 40 GHz, which matches well with the data from simulations. Test 1 and Test 2 are test coupons, while J5 and J6 are connectors on the board.

The cables used for the assembly are low-loss Sucoform™ semi-rigid cables from Huber Suhner with a GPPO connector on one end to connect to the 5081DX. The complete cable assembly has a return loss less than -15 dB up to 40 GHz and about 1 dB insertion loss. The complete 5081DX to board interface is shown in Figure 7.

4. Edge Launch Connectors: The 28821BR has Inphi-designed edge launch connectors which mate with standard 3.5 mm coaxial connectors. The interface to the PCB is modified to eliminate excitation of higher order modes, pushing the usage of these connectors well beyond 30 GHz. Figure 8 shows measured S-parameters of a single transition from cable to PCB, obtained on an 8510 VNA. The return loss remains below -14 dB, well above 30 GHz.

Conclusion
This article described the technical issues in the design of a novel integrated solution to high speed BER testing. We reviewed the challenges that arise due to the microwave frequencies involved in the board design, the use of appropriate high frequency connectors, and the design of the board to connector transition. The 28821BR Evaluation Board enables testing of high speed data patterns by allowing the user to electrically switch between four lanes of low speed data. It offers a simple and reliable solution for complete BER testing of components and systems by leveraging existing infrastructure of 10G BERTs, improving the return on investment for that equipment.

About the Author
Dhruv Jain has been a design engineer with Inphi since 2005. He has been engaged in the design and development of CMOS integrated circuits such as PLLs & DLLs for SERDES in high speed serial interfaces. He has also designed high frequency circuits in InP for 10-25 Gbps logic gates for Test & Measurement applications and Mach-Zehnder modulator drivers for 10 Gbps SONET applications.

Dhruv holds a B.Tech degree in Electrical Engineering from the Indian Institute of Technology, Bombay and a M.S. in Electrical Engineering from Stanford University.

Inphi Corporation
www.inphi-corp.com
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