LDMOS Amplifiers Exceed 50% Efficiency in W-CDMA Doherty Applications
By Leonard Pelletier, Application Support, Freescale Semiconductor

Wireless carriers are continuously seeking ways to reduce the annual operating cost of the transmitters in their base station transceivers, which consume the greatest amount of power at a typical cell site. The Doherty amplifier architecture commonly employed by most third-generation and emerging fourth-generation networks has inherent characteristics that significantly increase amplifier efficiency. However, to achieve their best performance, these amplifiers require RF power transistors that satisfy the requirements imposed by the Doherty’s unique architecture. Freescale Semiconductor’s eighth generation (HV8) of LDMOS RF power transistors have demonstrated their ability to exceed 50% efficiency in asymmetrical Doherty amplifiers over a broad bandwidth, while simultaneously achieving excellent system level linearity.

Demonstrating Higher Efficiency
The improvements offered by the HV8 devices are best demonstrated by measurements made on two asymmetrical Doherty reference designs, one for 900 MHz and another for 2100 MHz, when operated under the most stringent Doherty test conditions. Although the symmetrical Doherty configuration was used in base station transmitters until recently, the asymmetrical type has become the choice for most new designs. A symmetrical Doherty amplifier is optimized to produce its highest levels of efficiency at a -6 dB output back-off (OBO) from saturated (P-3 dB) output. In contrast, the asymmetrical design provides greater flexibility by allowing adjustment for peak efficiency over a -6 to -9 dB OBO range.

The impedances both inside the device and on the circuit board of the reference designs have been optimized to cover the complete range of typical drive-up conditions, back-off ratios, efficiencies, and peak RF output power levels expected in service. These reference designs, along with schematics, bills of materials, circuit board DXF files, tuning tips, product models, and typical RF performance parameters are available from Freescale to amplifier designers.
The 900 MHz version of the HV8 asymmetrical Doherty reference design (Figure 1) utilizes a MRF8S9120N LDMOS FET as a carrier amplifier operating in Class AB bias mode and an MRF8S9200N FET as the peaking amplifier in a very light Class C bias condition. The 28 V internally-matched MRF8S9120N delivers typical single-carrier W-CDMA performance of -36 dBc adjacent channel power ratio (ACPR) at the 33 W average output power level over a 3.84 MHz bandwidth with an input signal peak-to-average radio (PAR) of 7.5 dB. It delivers a typical P-1dB output of 120 W CW. The MRF8S9200N delivers 36 dBc ACPR at a 58 W average power level over a 3.84 MHz bandwidth with an input signal PAR of 7.5 dB. It can handle a 10:1 VSWR at 32 V with a +3 dB overdrive condition at 940 MHz and 300 W CW output power, and typical P-1dB output power is 200 W CW. Both devices incorporate ESD protection and wide negative gate-source voltage range for improved Class C operation.

The device combination produces an output power of 400 W at -3 dB gain compression (Psat) and has a 50% DC-to-RF conversion efficiency under 8 dB power-level back off conditions. Digital predistortion (DPD)-corrected output is -58 dBc ACPR at an output power of 63 W. With 7 dB OBO, the design has demonstrated efficiencies greater than 53%. Details are shown in Figure 2. Gain is flat and greater than 17 dB across the 920 to 960 MHz band.

The 2100 MHz version employs an MRF8S21120H LDMOS FET as a carrier amplifier in Class AB bias mode and a MRF8S21240H LDMOS FET as the peaking amplifier set for a Class C bias condition. The MRF8S21120H delivers typical single-carrier W-CDMA performance of -38 dBc ACPR at 28 W average power over a 3.84 MHz bandwidth with an input signal PAR of 7.5 dB. It can handle a 10:1 VSWR at 32 V, +3 dB overdrive at 2140 MHz and 160 W CW output power, and typical P-1dB output is 130 W CW.

The MRF8S21240H delivers typical single-carrier W-CDMA performance of -35 dBc ACPR at 56 W average power over a 3.84 MHz bandwidth with an input signal PAR of 7.5 dB. This Doherty combination produces 450 W at -3 dB gain compression with 50% DC-to-RF conversion efficiency at an 8 dB power back off and a DPD-corrected output of -58 dBc ACPR at a 70 W output power level. With 7 dB OBO, the design produces efficiency greater than 52%. Details are shown in Figure 3.

Improvements in Many Areas
Freescale has devoted significant development efforts to optimize the performance of its HV8 devices for use in Doherty amplifiers linearized with Digital Predistortion (DPD) technology. Important criteria such as AM/AM and AM/PM distortion, peak efficiency, peak power impedance locus, and characteristics over broadband RF sweeps, have guided the HV8 development process. HV8 device engineering directly contributes to maximizing Doherty efficiency while ensuring excellent linearity when coupled with DPD systems.

As a result, the efficiency of the HV8 devices is typically 4% to 6% higher in asymmetrical Doherty applications than previous generations of Freescale LDMOS devices, which reduces the overall daily operating expense of the base station. More important, HV8 enables a new generation of more compact and lighter Remote Radio Units (RRUs). They provide a more flexible and cost-effective way to deploy 3G and 4G networks but also require greater levels of energy efficiency as cooling is very limited. The RRUs also call for superior reliability as they are deployed in locations difficult to access compared to the traditional ground based base stations. The LDMOS process has been successfully deployed in the field for over 15 years and has proven to be an extremely reliable and rugged technology for RF power applications. HV8 builds on this legacy and brings additional margin in terms of ruggedness and long-term reliability.

Summary
Freescale continues to improve the performance of its HV8 family of LDMOS FETs to meet the needs of current and coming generations of wireless services. Measurement results of the two reference designs described in this article illustrate these enhancements. Looking into the future, performance gains based on the cost- effective LDMOS Doherty architecture are likely to occur as each system elements – LDMOS device technology, transistor matching components, and PCB design elements -- can all be further optimized to meet the challenges of 3G and 4G networks.

Freescale Semiconductor
www.freescale.com/rfpower
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