Synchronous Ethernet Timing Solutions. With Narrow Loop Bandwidth and Ultra Low Output Jitter
By Param Nampoothiri, Sr. Applications Engineer, Valpey Fisher Corporation

Introduction:
Today’s consumers demand more bandwidth and faster, more reliable services. Network providers are designing the next generation IP based networks to meet the demand and Ethernet has emerged as the transport medium of choice. Ethernet also gives more flexibility for integrating video, data, and voice.

For more accurate data multiplexing and de-multiplexing, IP based networks have a strong requirement for frequency synchronization across the entire network. SONET based networks have this capability already. A new solution is to take the already popular asynchronous Ethernet Network and synchronize it. This new technology is called Synchronous Ethernet or Sync-E. It will provide robust and reliable technology for applications where SONET is used today through accurate frequency synchronization.

Where Synchronous Ethernet (Sync-E) is Used
1. Wireless Backhaul
• For GSM systems, the timing reference has been T1 or E1 based. Bandwidth of these links is saturated due to the new 3G services.
• LTE – next generation wirless protocol
• Current GPS based systems – moving to Sync-E for frequency reference

2. Metro and Carrier Ethernet
• Circuit Emulation Services
• Digital Video Broadcasting

Technology
Synchronous Ethernet is a physical layer (PHY) frequency synchronization that is achieved through the Ethernet port. This method requires a primary reference clock (PRC) feeding the Ethernet Network. At each node a timing recovery unit will recover PRC, and use it as the transmit clock to the next node.

Figure 1 shows a standard synchronization method and the sync flow. In Node 1 the clock and data recovery (CDR) recovers the clock and data, passes the recovered clock (R_CLK) from the PRC. The R_CLK will have jitter and cannot be use as the transmit clock. The clock will pass through a phase-locked loop (PLL) to remove the jitter and to the clock multiplication unit (CMU) where it is used as the transmit clock (TX_CLK). The TX_CLK remains synchronized to the original PRC. The downstream CDR at Node 2 receives this clock and does the same process. The process of receiving and transmitting clock and data continues through multiple nodes in the network until it reaches its final destination. At each node the TX_CLK is synchronized to the PRC.

Primary standards for Sync-E:
• ITU-T G.8261 – Timing and synchronization aspects in packet network
• ITU-T G.8262 – Timing and characteristics of Sync-E equipment and slave clock
• ITU-T G.8264 – Distribution of timing through packet networks
• ITU-T G / 781 – Synchronization layer functions

Effects of Jitter in Sync-E
In Sync-E the clock is re-used at each node and jitter (noise) of the clock has great effect on the node. Two types of jitter are most problematic in synchronous systems: Jitter Transfer (the jitter passes through the node) and Jitter Generation (the jitter created by the node.

Jitter Transfer: This is the amount of jitter that passes through the node from the slave or R_CLK to master or TX_CLK. The R_CLK from the PHY is expected to have a large amount of jitter in it since it is coming directly from the network. Another important aspect of this jitter is it can be anywhere in the frequency spectrum. It could be close-in or far-out and it is not predictable.

Jitter Generation: This is the jitter created internally at each node by the system itself. The majority of this jitter is generated by the PLL, power supplies and other components in the individual node. Each node must limit the amount of jitter it generates internally otherwise the jitter from each node will add to the noise in the network and eventually the node will not meet the TX_CLK requirement.

Valpey Fisher (VF) Products for Sync-E Application
Valpey Fisher has developed a series of products for Sync-E applications that specifically address both Jitter Transfer and Jitter Generation issues. VF products use a “crystal based” internal reference clock and an extremely narrow loop filter to produce the best performance solutions available in the industry today.

Technology
To address jitter transfer, the internal loop bandwidth is reduced to the minimum level possible – typically below 10 Hz. By having this low bandwidth, the jitter transfer from input to output reduces to almost zero. In addition, an internal “crystal based” reference is used to provide a stable, jitter-free clock. The “crystal based” technology produces the least amount of jitter and sub-harmonics, while virtually eliminating the second major concern - jitter generation.

Key Advantages of VF Products
• Minimal jitter transfer
• Ultra low output jitter – 0.25 ps RMS
• Allows indefinite number of cascaded nodes
• Selectable input reference frequencies
• Multiple outputs (copies) available
• Lowest output jitter on the market
• Internal loop filter
• Internal voltage regulator for power supply
• Local ground plane eliminates ground loops
• Completely integrated solution lowers assembly and test costs
• High “Q” voltage-controlled crystal oscillator (VCXO) provides lower phase noise, excellent power supply rejection ratio (PSRR), and higher jitter budget

Phase Noise Plots:
Figure 4 is a phase noise plot of VF’s device, with a high jitter input clock (red). In this phase noise diagram, the red line is the input clock and blue line is the output clock. The red line has a lot of noise on it and a fairly high noise floor. The output (blue) tracks the input up to the loop bandwidth max (100 Hz offset) and then provides a clean, low noise output with a noise floor 25 dBc/Hz better than the input. Jitter is calculated from the area under the curve and in this example is significantly improved by the Valpey Fisher Jitter Attenuator.

Figure 5 shows the output phase-noise of the Sync-E product VFJA402. Output frequency is 156.25 MHz with 0.2 ps RMS Jitter!

Competitor solutions for Sync-E applications are based on Silicon PLL technology (see Figure 2) with an external reference clock, as shown in the Silicon Based PLL diagram.

The PLL uses the external clock for generating the required frequencies through the PLL. It uses the external loop bandwidth circuit (6 components) to reduce the amount of jitter it passes from the R_CLK to TX_LK. Unfortunately, Silicon Based PLLs are inherently “noisy” and the jitter generation may approach or exceed the 1.0 ps limit set by the PHY devices. Silicon Based PLL solutions have limited bandwidth so they can only block noise over a limited offset frequency (typically 12 kHz to 20 MHz) but cannot block the noise over the entire spectrum like a “crystal based” solution (see Figure 3) can. Since network noise and jitter are unpredictable, significant amounts may “transfer” outside of the 12 kHz to 20 MHz range and effect the performance of the PHY. Since jitter is additive throughout the network, too much of it limits the overall performance and may cause nodes to fail and reject incoming data.

VF Products in Sync-E Application
VF Sync-E products are typically used to eliminate the jitter from the output of the timing module which utilizes a Silicon based PLL; shown in the General Sync-E Block Diagram (see Figure 6).
The R_CLK from the PHY will connect to the timing module to generate the multiple clocks for the transmit path. This clock cannot meet the TX_CLK jitter requirements thus goes through VF’s product to limit the jitter transfer and provide the low jitter TX_CLK back to the PHY.
Valpey Fisher can provide a design guide and evaluation boards for all product types (see Table 1). Custom frequencies up to 2.4 GHz are also available. Please consult the factory.

About the Author:
Param Nampoothiri received his BSEE from the University of Calicut and his Master’s Degree in Engineering Management from the University of Ottawa. Mr. Nampoothiri is currently a Senior Field Applications Engineer at Valpey Fisher Corporation. He has more than 15 years of experience in account management, product development, and program management in the high-tech industry.

VALPEY FISHER CORPORATION
www.valpeyfisher.com
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