A New Concept in Frequency Synthesis
By Vitaly Koslov

A new concept in frequency synthesis permits the achievement of excellent spectral purity, high agility, very fine resolution, low power consumption and low cost. The principle of the Phase Digital Synthesizer (PDS) is that the control signal of the PLL is formed by a multi frequency-phase comparator with phase splitting of the reference and VCO signals into a large group of compared signals. The outputs of these partial detectors are then summed to develop the VCO control voltage.

I. Introduction
The most important characteristics of the frequency synthesizer are the agility and the spectral purity of its signal. It is critical that they be of a high enough level to obtain high quality telecommunication and measuring equipment. There is no necessity to review all possible variants of synthesizer structures because there is a detailed description of them in [1-3]. The types that merit special attention are Direct Digital Synthesizers (DDSs) and PLL synthesizers with variable ratio dividers in the loop. This is because the concept of synthesis proposed is based on such types of structures.

As it is known, the DDS synthesizers, while being very fast switching, do not provide good enough spectral purity to be used in a direct way in telecommunication and measuring equipment. The best samples, such as, for example, AD9858 from Analog Devices, have a guaranteed level of spurious signals (spurs) not better than -52dBc in the range of 180 MHz [4]. In order to get a frequency, e.g. 1000MHz, there needs to be additional means of multiplication or the inclusion of a DDS as a divider of variable ratio into a PLL and in consequence of that, the level of spurs rises to -37dBc.

The synthesizers based on PLL with divider of integer variable ratio in the loop [5-6], because of their well known disadvantages, are used only in the systems where there is no need to have very high specifications of frequency resolution, agility and spectral purity. The more recently developed synthesizers have fractional instead of integer ratio and means for compensation of fractional components with delta-sigma modulation (Fractional-N Synthesizers) [7]. The chips manufactured by Analog Devices Inc.[8], Synergy Microwave Corp.[9], and many others have low power consumption and cost, but also have low spectral purity (spurs) which not excels the same characteristics of AD9858. They have poor agility too because PLL bandwidth must be narrow enough (as a rule, some tens of kHz) to suppress quantization noise due to delta-sigma modulation, which increases steeply with increasing offsets from the carrier. It seems the most significant achievement in developing the Fractional-N method is achieved by designers from Hittite Microwave Corp. with the raising of comparison frequency to 105MHz and enlargement PLL bandwidth to 300kHz. However, they do not publish any data about spurs [10].

That is why in order to provide simultaneously high levels of agility and spectral purity they resort to multi-loop structures which are bulky, expensive, and have greatly increased power consumption.

The goal of this article is to show that not all possibilities in developing single-loop synthesizers are exhausted, and that there are such variants of schematic composition which could realize simultaneously the advantages of the all units of such type existing on the world market today. It is the agility of DDS, low cost and low power consumption of the Fractional-N synthesizer, and high spectral purity of the multi-loop system.

Further, the new type of synthesizer is named PDS – Phase Digital Synthesizer, for short.

II. Description of the New Principle of Frequency Synthesis
The idea of the PDS synthesizer can be explained by one of its versions shown in Figure 1.
In this variant for compensation of fractional components delta-sigma modulation (DS) is used, and the variant is named as PDS-DS.

There is an accumulator, clocked by reference frequency fr and having, for example, n=32 of most significant and least significant bits (MSBs and LSBs), respectively, coupled to each other by a carry network. The number of bits in the blocks can be, for example, k=5 and n-k=27 bits, respectively. Data inputs D of MSBs and LSBs blocks (codes R1 and R2) are connected to a HOST unit (user input) which generates the frequency tuning word R=R1+R2 determining the synthesizer carrier and direct FSK and PSK modes.

A Phase Splitter generates on its K=2k outputs the pulse sequences of frequency Fr=Rfr/q, on average, where q=2n. Each of the sequences is an exact copy of all accumulator overflow, and the sequences are shifted in time respectively to each other by T/K, where T=q/fr. In fact, all the sequences are the result of dividing the reference frequency fr by a fractional value q/R. In other words, there are as if formed K, for example K=32, overflow outputs of the accumulator, and these outputs are shifted in time.

Thus, the phase splitter forms the K reference sequences for the PLL. The latter contains, in consecutive order, a voltage controlled oscillator (VCO), loop divider (:N, if it is necessary), pulse distributor, phase comparator, simplest digital-to-analog converter (KR-ladder), and a low pass filter (LPF). The output of the VCO is the output of the synthesizer.

In order to be able to phase compare the signal with the reference sequences from the phase splitter, there is the need to generate, in the pulse distributor, the analogous sequences from VCO. In one of the possible versions, it is fulfilled in the same way as it was explained above, i.e. the pulse distributor contains an accumulator of the same MSBs mentioned above, capacity Q=K, and a phase splitter, both clocked by signal pulses fc. The accumulator has a code C on its input which can be both constant and variable, and thus the pulse distributor forms on its Q=K outputs the K periodic or quasi-periodic-pulse sequences (depending on whether numbers K is divisible by C or not) of frequency Fc=fcC/K, on the average, and these sequences are shifted in time relative to each other.

The phase comparator (in fact, it is a phase detector – PD) can be a set of RS flip-flops, the number of which is K. The S-input of each RS flip-flop is connected to one of the K outputs of the phase splitter. The R-inputs of the RS flip-flops are connected to the Q outputs of the pulse distributor. If Q=K, as it was assumed above, then the R-input of each RS flip-flop is connected to the corresponding one of the K outputs of the pulse distributor.

In another version, if in the simplest case the input number C of the accumulator is set to 1, then this structure is the equivalent of a ring counter. Its capacity Q can be less than K, for example Q=4, as it is shown in Figure 1. The latter is a simple device which is convenient in practice. In this version, all RS flip-flops should be subdivided into Q number of batches, with K/Q flip-flops in each batch. In each batch, all R inputs of the flip-flops are connected to a corresponding output of the ring counter.

The duration of pulses on the RS flip-flop outputs depends on phase differences of the pulse sequences from the outputs of the phase splitter and pulse distributor. After being passed through the KR-ladder and the LPF, the pulses are transformed into the voltage for controlling the frequency of the VCO. Thus, each of the RS flip-flops with the corresponding segment of the KR-ladder operates as a partial phase detector, bringing its own portion into the full scale of the control voltage.

By the action of the PLL, there is provided an equation Fc=Fr, i.e. fc=NQfrR/q. In the example of Figure 1, for providing 600..1200 MHz band with reference fr=1000 MHz, there is N=1; Q=4; and frequency tuning word is changing within octave (from R=00100,11... to R=01001,10...). In order to get the next octave bands, the value N can be changed to 2, 4 and so on.

For compensation of fractional noise there is a Delta-Sigma (DS) block which modulates the contents of the accumulator. The DS block is a well known structure which is used, for example, in Fractional-N synthesizers.

It will be appreciated that each changing of accumulator contents, generated by the DS block, also changes the current value of code on the MSBs bit outputs, and thus shifts the phase of pulses on the inputs of RS flip-flops in the phase comparator, causing the corresponding response on the output of the latter.

The delta-sigma modulation acts, in even distribution manner, on each segment of the KR-ladder. So if there is inaccuracy in any one of them, then it results in a spurious spectrum, having corresponding distribution of components. As a result of a large enough number of the segments, the influence of each segment inaccuracy on the level of total spurious components is lowered.

The main advantage of PDS structure is that there is no need to have a fractional divider which is indispensable in a Frac-N synthesizer and hence lowers the comparison frequency. As it is shown in Figure 2, in the PDS synthesizer each pulse of signal frequency is phase controlled by the phase comparator, and each pulse of reference frequency, through the phase comparator, works to phase control the signal pulses.

In other words, it is as if the division in PLL loop is the equal of N=1.

That is why the bandwidth of PLL can be chosen to be as wide as required to suppress the noise of the VCO and/or to provide desirable fast switching speed.

The KR-ladder is a simple device which can be fulfilled as a set of resistors of modest accuracy, say dA=1%.

At the same time, if there is a need for using the synthesizer in mobile or other systems where low power consumption is very important and agility is of lesser importance, then the consumption can be lowered at the expense of agility.

In this case, there is included a frequency divider of ratio M for lowering by M times the clock frequency for the block of least significant bits of the accumulator and the DS block.

Lowering clock frequency of these blocks results in significant power consumption savings because a considerable share of the synthesizer logic falls within these blocks.

It is obvious enough that in this case the fractional noise characteristic in the low frequency area remains about the same, but in the higher frequency area the noise is increased, so the PLL bandwidth has to be narrowed by the same relative amount, and thus the agility of the synthesizer is lowered by the same amount. It is important to note that the factor of noise multiplication remains the same low value because the main reference, for MSBs, remains of the same high value.

In Figures 3 and 4 there are the diagrams of integrated phase noise in PLL bandwidth for the cases when fr=1000 MHz and signal frequency fc is brought to 1000 MHz. They illustrate that it is no problem to provide PLL bandwidth of 10 MHz and more, i.e. there is a possibility for direct very high bandwidth FSK and PSK with very high spectral purity.

Though in Figures 3 and 4 the values of fr and fc are constant, fr= fc=1000MHz, the results can be recalculated, without any difficulty, for any values of fr, fc and M in order to evaluate the advantages of this synthesizer in providing super-high agility and spectral purity, or low power consumption with super-high spectral purity and good enough agility.

Another version of PDS is shown in Figure 5.

The only difference is that instead of the DS block for compensation of fractional noise, there is a R2R-ladder coupled to the output of LSBs block, and the output of the KR-ladder is fed to a common point of the KR-ladder configuring the completed DAC. This version can be named the PDS-R2R synthesizer. The advantage of this version is that DS-block is eliminated and thus the power consumption is lowered.

Of course what is shown in Figure 5 is the conventional form of DAC. In practice it can be implemented with the foremost technology. The less DAC inaccuracy, the less residual fractional noise remains. Theoretically, the noise is removed entirely with a DAC of ideal accuracy whereas in the PDS-DS version, it remains even if the KR-ladder is ideal (see diagrams “0%” in Figure 3).

More detailed information about this version can be obtained from [11].

III. Conclusion
The analysis presented above shows the superior possibilities of the concept in frequency synthesis proposed. Described schematics, being implemented in integrated chips, would allow creation of the simple single-loop synthesizers which feature agility and spectral purity not worse than complicated multi-loop structures have, and at the same time cheaper by an order of magnitude and with significantly less power consumption.

References
1. Kroupa, V., Frequency Synthesis Theory, Design and Applications, Hoboken, NJ, John Wiley & Sons Inc., 1973.
2. Manassewitsch, V., Frequency Synthesizers Theory and Design, Third Edition, Hoboken, NJ, John Wiley & Sons Inc., 1987.
3. Chenakin, A., "Frequency Synthesis: Current Solution and New Trends," Microwave Journal, May 2007.
4. 1 GSPS Direct Digital Synthesizer AD9858, Data Sheet, Analog Devices Inc., www.analog.com.
5. Young, C., US Patent #2,490,500, Cl.331-25, 06.12. 1949.
6. Woodward, US Patent #2,490,499, Cl.331-26, 06.12. 1949.
7. Wells, John N., Frequency Synthesizer, Cl.O3L 7/00, 02.09.1986.
8. Wideband Synthesizer with Integrated VCO – ADF4350, Data Sheet, Analog Devices Inc., www.analog.com.
9. Fractional-N Synthesizer, Articles, Synergy Microwave Corp., www.synergymwave.com.
10. 8 GHz 16-bit Fractional-N Synthesizer, Products, Hittite Microwave Corp., www.hittite.com.
11. Koslov, Vitaly, Digital PLL Frequency Synthesizer, US Patent #5,748,043, 05.05.1998.

About Author
Since 1960, Vitaly Koslov has worked as a designer engineer for several R&D institutes in the former Soviet Union. He published articles in “Electrosvyaz” and “Radiotechnica” – the main sci-tech journals of Russia. He currently works as a consultant serving a number of companies in Russia, Ukraine and the United States and is a candidate of Science. He can be reached at vkoslov@yandex.ru

VITALY KOSLOV

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