Hittite’s 18 GHz Ultra Wideband Track-and-Hold Amplifier Enhances High Speed ADC Performance
By Hittite Microwave
Wideband data acquisition systems with multi-GHz bandwidth are needed for a variety of applications such as software defined radio, radar systems, Electronic Warfare (EW) / Electronic Intelligence (ELINT) and test and measurement equipment. Ideally, system designers would like to be able to connect the signal source (for example an antenna) directly to a wideband, high dynamic range Analog-to-Digital Converter (ADC) for digitization.
Many of these applications involve sub-sampling where the signal of interest is a high frequency signal well beyond the ADC sample rate. A key limitation to this approach is that current ADCs do not generally have sufficient bandwidth for these wideband applications.
Although several high speed ADCs offer enhanced sample rates, few of them offer input bandwidth beyond a few GHz. In addition, maintenance of good sampling linearity at frequencies above the UHF band is technologically challenging and most current ADCs suffer rapidly degrading linearity above 1 or 2 GHz signal frequency. These limitations result from the Track-and-Hold Amplifier (THA) which sample the input signal at a precise time instant and holds the value of the sample constant during the analog-to-digital conversion. This THA (integrated into the ADC) is often not optimized for ultra wideband operation. These limitations can be overcome by using Hittite’s HMC5640BLC4B Ultra Wideband Track-and-Hold Amplifier, which is designed for use in microwave data conversion applications requiring maximum sampling rate, low noise and high linearity over a wide bandwidth.
The HMC5640BLC4B, which offers 18 GHz input bandwidth and excellent broadband linearity, is used as an external master sampler at the front end of an ADC. Once extended bandwidth sampling takes place within the HMC5640BLC4B, the low bandwidth held output waveform can be processed by an ADC with substantially reduced bandwidth. ADC converter linearity limitations at high input frequencies are also mitigated because the settled THA waveform is processed with the optimal low frequency linearity of the ADC. Additionally, the HMC5640BLC4B offers very low random sample jitter of typically <70 fs, which minimizes jitter induced Signal-to-Noise (S/N) ratio degradation at high microwave signal frequencies. This jitter performance is significantly better than that typically exhibited by currently available ADCs. The result is a radical extension in input bandwidth, substantial improvement in high frequency linearity and improved high frequency S/N ratio for the THA-ADC assembly compared to the performance of the ADC alone.
HMC5640BLC4B Ultra Wideband Track-and-Hold Overview
An HMC5640BLC4B evaluation board is shown in Figure 1 while Table 1 summarizes some key performance parameters. Unlike other available high speed THAs, which suffer substantial bandwidth degradation at full scale input levels, the HMC5640BLC4B provides 18 GHz sampling bandwidth over the full range of input level up to a full scale differential input of 1 Vp-p and up to 4 GS/s sampling rate. The THA maintains excellent linearity over a very broad bandwidth with 56 dB or better Spurious Free Dynamic Range (SFDR) from DC to beyond 5 GHz at full scale input. Users may perform post conversion processing to reduce the wideband noise floor and may choose to tradeoff input signal level for higher linearity. A reduction of input level to half full scale results in 10-bit or better linearity across a wide bandwidth (Table 1). The large signal bandwidth, broadband linearity and high sampling rate of the HMC5640BLC4B are superior to other commercially available THAs.
The HMC5640BLC4B provides DC-coupled, differential signal I/Os and differential clock inputs. All I/Os are 50 Ohm impedance for each differential half circuit and operate at true ground-referenced common mode potential. The HMC5640BLC4B is housed in a RoHS compliant 4 x 4 mm QFN leadless ceramic package. Suitable applications include software defined radio, military and commercial radar systems, EW and ELINT systems, spread spectrum processing, wideband spectrum analysis and high speed digital and analog test instruments including digital sampling oscilloscopes.
Performance of the HMC5640BLC4B Track-and-Hold with a Commercially Available 1.6 GS/s, 12-Bit Dual ADC
The HMC5640BLC4B is a single-rank THA which is optimized as a master sampler for high speed ADCs. For equal technologies and designs, a single-rank device will have better linearity and noise than a dual-rank device, since the single-rank has fewer stages. Since high speed ADCs already have an internal THA, normally with much less bandwidth, the HMC5640BLC4B forms a composite dual-rank configuration with the THA in the converter.
A block diagram of a typical application using the HMC5640BLC4B as a master sampler for a high speed 1.6 GS/s, 12-bit dual ADC is shown in Figure 2. This figure also corresponds to our THA and ADC evaluation board set-up that was used to demonstrate the performance enhancement delivered by the HMC5640BLC4B THA. A variable delay line properly phases the ADC clock so the ADC samples the hold-mode portion of the output waveform from the HMC5640BLC4B. When using the HMC5640BLC4B in an actual system, it is preferable to place the THA in close proximity to the ADC to minimize the transit time of reflection effects on the interconnect between the devices.
As we demonstrate here, however, a breadboard type setup with coaxial cable interconnects can give acceptable performance when the ADC clock is properly timed with respect to the THA clock. For this demonstration, only one of the two ADCs on the chip are driven by the THA and the performance of the composite THA-ADC assembly, as well as the ADC alone, is measured in non-interleaved mode for both
1 GS/s and 1.6 GS/s sample rates. Input signal RF amplitudes are precisely leveled across frequency, producing ADC signal outputs in the range of 0 to -1 dBFS for all measurements. The PC software provided with the ADC reference board is used for the ADC output data acquisition and spectral analysis.
As shown in Figure 3, the 18 GHz bandwidth HMC5640BLC4B radically enhances the sampling bandwidth well beyond the intrinsic 2.8 GHz ADC bandwidth. The small ripples in the frequency response are caused by small levels of reflections on the evaluation board and cable interconnects between the THA and the ADC chips. Even with these perturbations, which would be reduced in an integrated board implementation, the response is flat to approximately ±0.5 dB across 12 GHz.
The time domain S/N ratio and SFDR for the ADC alone and the THA-ADC combination at 1 GS/s and
-0.75 dBFS input level are shown in Figure 4. Comparison of the SFDR curves shows that the HMC5640BLC4B not only enhances the SFDR beyond the bandwidth of the ADC but also enhances it for frequencies within the 2.8 GHz ADC bandwidth by up to 11 dB. This enhancement occurs because the HMC5640BLC4B takes on the task of linearly sampling the high frequency signals and the constant amplitude, held output waveform presented to the ADC mitigates the slew-rate-dependent distortion created within the ADC’s internal THA.
The expansion of the front- end bandwidth to 18 GHz creates an unavoidable increase in noise floor for the THA-ADC combination at low frequencies where the ADC thermal noise tends to dominate. The ADC noise degradation created at higher input frequencies by the digitization noise is actually mitigated by the THA signal conditioning. This mitigation can be seen in the improved S/N ratio for the THA-ADC combination above approximately 3 GHz signal frequency. The HMC5640BLC4B THA mostly preserves the inherent equivalent input noise spectral density of the ADC. The difference in noise levels at baseband (250 MHz) is about 8.5 dB compared to the 8.1 dB ratio of the bandwidth expansion (10 log (18/2.8)=8.1 dB). The decreasing S/N ratio with increasing frequency of the THA-ADC combination is due to random sample jitter resulting from about 70 fs of HMC5640BLC4B THA jitter and about 54 fs of clock generator noise induced jitter (total sample jitter approximately 88 fs). In an optimized system, the clock filter bandwidth (5% fractional bandwidth = 50 MHz in this test setup) would be reduced to a much narrower bandwidth to reduce the impact of the generator noise, thus approaching an overall jitter level dominated by the 70 fs THA jitter.
Users performing post conversion signal processing are usually concerned about the noise floor reduction that can be obtained through averaging processes, either arising from direct averaging of multiple data records or the processing gain resulting from spread spectrum processing. Figure 4 shows that 10 averages of the complex FFT data reduces the noise floor by about 9 to 10 dB (while holding signal constant), demonstrating that the THA noise floor is truly random and behaves well under averaging, in accordance with our expectations, since it is a linear analog device with white noise floor. The lower frequencies tend to show averaging improvement of only 9 dB. This improvement reduction relative to the ideal 10 dB is caused by the ADC noise floor contribution, which does not completely average according to expectations once the averaged ADC noise gets into the vicinity of -63 dBc. Similar performance trends for S/N ratio and SFDR are obtained at a clock rate of 1.6 GS/s as shown in Figure 5.
These results demonstrate that Hittite’s HMC5640BLC4B Ultra Wideband THA can radically extend the bandwidth of existing high speed ADCs while providing enhanced high frequency linearity and noise performance relative to that obtained with the converter alone. For the tested converter at 1 GS/s, the HMC5640BLC4B provides Effective Number of Bits (ENOB) improvement beyond 3 GHz. At 1.6 GS/s the THA provides an ENOB improvement beyond 2 GHz. Similar performance enhancements have also been measured for another commercially available 1 GS/s ADC. This performance enhancement should be useful in a variety of applications requiring A/D conversion at wide bandwidths or high center frequencies that are beyond the reach of the existing high speed converters. Product data sheets and application notes for the HMC5640BLC4B are available at our website. Contact email@example.com with your Data Converter custom solution requirements.
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