IN MY OPINION

Evolving at the Speed of Software
By Sherry Hess, VP of Marketing,
AWR Group, NI

Thank you, Dr. Joe Salvo of GE Global Research and the founder and director of the Industrial Internet Consortium for sharing this tagline with me. At NIWeek 2014, Dr. Salvo took the keynote stage to comment on the Industrial Internet in the “systems age,” which has superseded the information age.
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MILITARY MICROWAVE DIGEST


MMD March 2014
New Military Microwave Digest

ON THE MARKET


Band Reject Filter Series
Higher frequency band reject (notch) filters are designed to operate over the frequency range of .01 to 28 GHz. These filters are characterized by having the reverse properties of band pass filters and are offered in multiple topologies. Available in compact sizes.
RLC Electronics


SP6T RF Switch
JSW6-33DR+ is a medium power reflective SP6T RF switch, with reflective short on output ports in the off condition. Made using Silicon-on-Insulator process, it has very high IP3, a built-in CMOS driver and negative voltage generator.
Mini-Circuits


Group Delay Equalized Bandpass Filter
Part number 2903 is a group delayed equalized elliptic type bandpass filter that has a typical 1 dB bandwidth of 94 MHz and a typical 60 dB bandwidth of 171 MHz. Insertion loss is <2 dB and group delay variation from 110 to 170 MHz is <3nsec.
KR Electronics


Absorptive Low Pass Filter
Model AF9350 is a UHF, low pass filter that covers the 10 to 500 MHz band and has an average power rating of 400W CW. It incurs a rejection of 45 dB minimum at the 750 to 3000 MHz band, and power rating of 25W CW from 501 to 5000 MHz.
Werlatone


LTE Band 14 Ceramic Duplexer
This high performance LTE ceramic duplexer was designed and built for use in public safety communication and commercial cellular applications. It operates in Band 14 and offers low insertion loss and high isolation to enable clear communications in the LTE network.
Networks International

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July 2012

Can’t RF and Mixed Signal Components Just Get Along? Overcoming the Challenge of RF Level Planning that Incorporates Mixed Signal Components
By Eamon Nash, Applications Engineering Manager, RF Products Group
Analog Devices, Inc.

One of the challenges of modern RF Level Planning is that the specifications of mixed-signal devices such as ADCs and DACs do not easily fit into the standard RF equations for calculating cascaded performance. When a designer tries to add ADCs and DACs—and some other components such as ADC drivers, IQ Modulators and IQ Demodulators—into an RF signal chain calculation, the non-50-Ohm impedances and the voltage-centric specs of the mixed signal components can make the task quite challenging. This article will address some of these challenges and will showcase the ADIsimRF® software tool which simplifies this task.

Every wireless signal chain design begins with signal chain choices. Once a systems engineer has decided on a signal chain architecture (e.g. Superheterodyne, Zero IF, IF Sampling, etc.), components must be selected. In a signal chain composed of discrete devices, it is critical to select components with comparable specifications. But it’s not as simple as picking devices that have some minimum level of performance. The effect of a device’s noise and distortion on the overall signal chain is a strong function of its gain and location in the signal chain. For example, the noise of a first stage Low Noise Amplifier will strongly impact the overall noise figure, whereas the noise of an Intermediate Frequency amplifier will have less of an impact.
To understand how individual components contribute to overall performance, systems engineers use the four classic equations shown in Figure 1, represented here for a 3-stage signal chain.

Figure 1: Cascaded Noise Factor, IP3, Gain and P1dB Equations for a 3-Stage Wireless Signal Chain

Gain can be easily calculated in the linear domain by multiplying the individual gains or in the log domain by summing the dB gains. However, composite Third Order Intercept (IP3), 1 dB Compression (P1dB) and noise figure must be calculated in the linear domain by converting P1dB and IP3 to Watts (from dBm) and by converting noise figure to noise factor (Noise Figure = 10log(Noise Factor)).

System engineers traditionally use home-grown spreadsheets or RF simulation tools to perform these calculations. One notable limitation of these equations is that they assume a perfectly matched signal chain with no impedance discontinuities between components. In real-world systems, inter-stage impedance mismatches are not uncommon, and in some cases they are deliberate.

Figure 2 shows a screen shot of ADIsimRF, an RF signal chain calculator which is available free from Analog Devices. At its core, this tool implements the cascaded equations for Gain, Noise Figure, IP3 and P1dB shown in Figure 1 along with power consumption. The number of stages can be dynamically varied up to a maximum of 15. Additional stages can be inserted at any point in the signal chain and individual stages can be deleted or temporarily disabled.

Figure 2: Using ADIsimRF to level-plan a Zero IF Discrete Transmitter

ADIsimRF includes an embedded database of ADI’s discrete RF components. This database, which also includes models for passive components such as baluns and SAW filters, can be easily accessed using pull-down menus as shown in Figure 2. Device data (IP3, P1dB, Gain and Noise Figure) are stored in the database at various frequency increments. When a particular frequency is selected, the calculator uses the closest frequency data point in the database. Data from the internal database can be overwritten on the calculator’s front panel and custom devices can be created and saved.

Performing level planning using components that are not simple 50-ohm, 2-port devices can be challenging. For example, an IQ modulator has three inputs, I,Q and LO. This raises the question of how to define its gain. In addition, the I and Q inputs typically have high input resistance, which makes it difficult to define their power gain.

An IQ modulator is generally driven by a Dual DAC with a Nyquist Filter between the two. This filter is terminated with two shunt resistors at the I and Q inputs. These resistors are typically between 100 ohms and 1000 ohms, with the size of the resistor scaling the DAC voltage up or down. In order to give the IQ modulator an effective Power Gain, ADIsimRF considers these resistors to be part of the IQ modulator. As a result, IQ modulator Gain in ADIsimRF is defined as the difference between the power delivered to each shunt resistor and the RF output power.
In the case of some IQ modulators, multiple models with different input resistances are provided in the ADIsimRF database. With an output resistance of 50 ohms and an input terminating resistance that ranges from 100 ohms to 1000 ohms, the power gain and the voltage gain of the IQ modulator will be different.

Defining the noise figure of an IQ modulator is also not obvious. If we define the power gain of the IQ modulator as above, then the noise figure can be defined as the difference between Thermal Noise (-173.8 dBm/Hz) and the Output Noise of the IQ modulator minus the Power Gain. So the Noise Figure of an IQ modulator with a noise floor of -157.8 dBm/Hz and Power Gain of 3 dB is equal to 13 dB (i.e. -157.8 dBm/Hz = -173.8 + 3 + 13).

Modeling mixed-signal components such as Analog-to-Digital and Digital-to-Analog Converters (ADCs, DACs) in an RF signal chain calculator is even more challenging. This is because a DAC does not have an obvious “Gain” and because the noise and distortion of a DAC change with sampling rate, data interpolation rate and dBFS drive level.

In the ADIsimRF tool, the “Gain” of a DAC is defined as 0 dB for a 0 dBFS drive level when the output is at baseband, that is, centered at 0 Hz. When a lower dBFS level (e.g. -6 dBFS) is chosen, the Gain will be lower by that amount. Also, as the DAC’s output frequency increases, the Gain will decrease as the DAC output follows the Sin(x)/x function.

To accommodate different DAC configurations, the ADIsimRF database includes a number of “versions” for each DAC (e.g. AD9122V1, AD9122V2, etc). Each version corresponds to different operating configurations, which include various dBFS drive levels, sample rates and interpolation rates.

The dual, differential, high-speed DACs that are used to drive IQ modulators are generally terminated with four 50-ohm resistors to ground. The DAC’s output current flows through these resistors along with the input shunt resistance at the IQ modulator inputs. In ADIsimRF, the output power level of the DAC is the power that is delivered into the shunt resistors at the IQ modulator.

Figure 3 shows a screen shot of a level plan for a 2.5-GHz IF sampling receiver. In this receiver, the input signal is amplified and mixed down to 140 MHz before being under-sampled by an ADC. The IF stage includes the AD8375 ADC driver, whose gain can be set in 1-dB increments from -4 dB to +20 dB. A pull-down menu can be used to choose any of the 25 available gains as shown in Figure 3.

Figure 3: An IF Sampling Receiver with impedance mismatches between some of the stages.

Like DACs, fitting an ADC into a RF signal chain calculator is not trivial. One common problem stems from the fact that the input impedance of ADCs and the amplifiers that drive them are not always matched. In the case of the AD9430 ADC, its internal input impedance of 3 kohms has been shunted down to 200 ohms using an external resistor connected across the differential inputs (the stored model in the ADIsimRF database for this ADC calls out an input impedance of 200 ohms). However, in this case there is still a mismatch between the ADC input impedance and the output resistance of the ADC driver and anti-aliasing filter. ADIsimRF takes account of this mismatch and adjusts the cascaded results accordingly.

Conclusions
ADSimRF is an easy to use level planning tool which can replace home-grown spreadsheets. In addition to calculating Gain, IP3, P1dB and Noise Figure, it also calculates power consumption and many voltage domain specifications such as rms and peak-to-peak output voltage. The task of including DACs and ADCs in calculations is made easier by including RF model data for these devices and through support for inter-stage impedance mismatch loss.
ADIsimRF operates on Windows XP, Windows Vista and Windows 7. It can be downloaded for free from www.analog.com/adisimrf

About the Author
Eamon Nash is an Applications Engineering Manager in Analog Devices’ RF Products Group. He has worked at Analog Devices for 22 years, first as a Field Applications Engineer, covering mixed signal products, then as an Applications Engineer specializing in discrete RF components for wireless applications. He holds a Bachelor of Engineering degree (B.Eng) in Electronics from University of Limerick, Ireland.

Analog Devices, Inc.
www.analog.com
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A federal agency like DARPA is a sitting duck for politicians and assorted other critics. It has come up with some truly bizarre programs over years that ultimately either delivered no tangible results, were canceled before they could cause any damage, or attempted to answer questions that nobody was asking or needed answers to. Read More...


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