Low Noise Amplifier Design Methodology Summary
By Ambarish Roy, Skyworks Solutions, Inc.
Low Noise Amplifiers (LNAs) amplify weak signals received by the antenna in communication systems. Every wireless system module typically consists of one or several LNAs. Applications include GPS receivers, wireless data systems, satellite communication, cellular handsets, radio systems, etc. The low noise in the receive chain is reduced by the gain of the LNA and therefore its function is primarily to amplify the incident signal power while adding minimum noise and distortion to the signal. The lower the noise figure (NF) of the LNA, the more the reception of the received signal is improved. Skyworks’ MMIC product portfolio incorporates sub-dB NF, high linearity LNAs which are compact, highly efficient and include great performance from enhancement mode (E-mode) pHEMT amplifiers. This article highlights the designing methodology of an LNA by focusing on their product realization process.
Development of LNA from process selection to modeling techniques has been covered.
To downselect an existing LNA or design a new one, the primary task is to understand the device’s electrical specifications required for the application. Along with application comes the frequency range of interest within which the amplifier will satisfy its performance on various electrical specifications. Typical electrical specifications are tabulated in Table 1.
Application requirement will dictate the packaging details of the LNA. Application may require a discrete LNA which can be tuned using passive external SMT components. With every discrete LNA product, Skyworks’ application team provides a well-tuned bill of materials (BOM) for a particular band. The same surface mount technology (SMT) BOM may either satisfy one or multiple bands which boils down to the choice of a design for the product, incorporating narrow band or broad band applications.
Integrated LNAs are the next generation modules comprising a complete tuned LNA inside a package. The BOM is therefore significantly reduced and this forms a one-drop solution for the customer’s application. There is, however, provisions provided on the printed circuit board (PCB) or evaluation board (EVB) which comes with the module to enable the customer to improve stability through external direct current (DC) bypass capacitors for careful tuning of the module on their system level circuitry.
Every discrete or integrated LNA will have a printed circuit board layout on which the BOM is mounted. Very few external components or a full BOM can be present. This generates flexibility from the customer’s system level prototype down selection. There will be a discussion of examples of discrete and integrated LNAs in later sections of this paper. Although the LNA’s stability at all frequencies is obtained from die level design, additional external bypassing to both the VDD and VBIAS bias lines could be added to the BOM in the form of a 10,000 – 100,000 pF capacitors.
Top Level Design
Typical block diagrams of discrete and integrated LNAs are shown below in Figures 1 and 2 respectively. An example of a BOM is also illustrated in Figure 3 where the LNA is still a discrete part but has been designed to perform for a specific frequency range using the external tuning schematic. The external match for integrated designs can be very little but compared to a discrete LNA for a particular band, the performance may be slightly compromised if compared.
Top level design includes basic architecture, package size, and pin layout, which can be either from general market specification or specific customer related. With a good portfolio of LNAs, a designer may choose to modify existing designs or create a new one based on the specificity of the demanded performance. With several foundry technologies available to the designer, the push is always towards exceeding the performance with a family of new products. Skyworks’ portfolio, for example, covers several ultra-low noise amplifiers.
Packaging Level Design
A level below the top level design, we will describe the model for the package on which the die is assembled. Integrated LNAs have more complexity with routing paths and metal pads than discretes. However, they both have common parasitic elements which need to be extracted through electromagnetic (EM) modeling of the package. An illustration of the parasitic modeling for the integrated LNA and a discrete LNA has been shown in Figures 4 and 5 respectively.
This packaging level modeling includes package substrate dielectrics, bondwires with accurate thickness, lengths and passivation layers. Every parasitic contribution has to be accounted for to generate accurate simulation results, which enable designers to release first pass success prototype parts. For example, the bond wires which contribute to parasitic inductance and resistive losses affect gain and, therefore, the noise figure. They also affect the stability of the LNA very critically. Therefore, proper tuning initially is very important.
Die Level Design
LNA design can be obtained from different architectures of single or multiple field effect transistors (FETs) connected together. The most common is the cascode architecture with its various forms. Cascode architecture provides the best isolation between the input and output RF ports. Other architecture examples include cascade, differential, Darlington, and folded cascode.
FET models are provided by the foundry after matching measured data from varying peripheries of the FETs. Models of varying periphery FETs from measured data are generated from over varying gate and drain voltages. Prediction from FETs is very accurate if the designed FET in the LNA is operated carefully around those modeled bias conditions. These targeted operating conditions assure a good performance from both small and large signal of the designed LNA.
Apart from the LNA FET models, there are numerous passive elements including the routing which takes precedence over the parasitic contribution. Every path which connects and transfers RF signals should be thoroughly solved using EM simulations. For EM simulations, designs in ADS can utilize momentum simulations; designs in cadence can use EMX. In addition, if the models through HFSS, passive elements can be simulated in HFSS as well. Various choices remain with the designer based on the availability of their respective process design kit (PDK).
An example of a modeled inductor is shown in Figure 6. Capacitors, resistors and routing/connections in between the active and passive elements are also EM solved. It is, however, advisable to solve the whole die level passive routing and elements together to obtain a full EM environment and the solved S-Parameter file can be thereafter used in the design with the FET models. This procedure is very important to assure proper LNA operation designed for a strict performance. Another important aspect which gets benefit from solving an LNA design in EM is the stability observations of the device. Through EM, the losses of the traces and the elements can generate enough information which can lead the designer to obtain an LNA design with unconditional stability. An excellent LNA performance without good stability will not make it as a product. There are instances when a LNA with good stability could fail to be stable at the customer system evaluation board. EM experience from the particular LNA is therefore, a plus.
For small signal designing, the external or internal tuning match can shift the response to the desired frequency band. The gain control vs. NF is another challenge with the LNAs. For minimum NF, the intrinsic gain of the LNA should be realized but usually some compromise is acceptable to meet customer’s specification. For large signal, there are different ways to tune the performance but the most common is through the dc operating conditions of the FET. An example is shown in Figure 7 where there are two designs with different transconductance (gm) curves. The blue curve is superior in terms of large signal performance where there is a flat zone of the gm curve. Published and measured researches have shown that intermodulation products can be cancelled to a higher degree with flat gm curves, and if the FET is correctly biased at the flat zone, the large signal performance can be significantly improved.
System Level Design
Once the LNA qualifies as a product, Skyworks’ application team will deliver the part’s S-parameters files along with their BlackBox models. Customers can insert these BlackBox models of any of the LNAs into their system level simulations and predict the small/large performance. They may also evaluate the ADS project provided with the BlackBox models which comprises the application board simulation and verify measured vs. simulated data of the respective LNA. For quick prototype selection, S-parameters file along with the NF performance of the LNA, will be the quickest way to describe the RF behavior of a component over frequency under any simulation platform.
Skyworks Family of Products
Skyworks’ MMIC product portfolio in enhancement mode (E-mode) pHEMT amplifiers is large. The LNAs cover multiple frequency bands. Some of them have been specifically tuned for a broadband match as well. Every LNA has been carefully designed keeping the best performance from their respective frequency band. After PCB placement and mounting SMTs from the BOM, these LNAs achieve their best performance.
Some of the family of products are presented here in Table 2, illustrating high performance, LNA modules designed for use at 0.03 to 3.6 GHz wireless applications. Targeted applications are mainly GSM, CDMA, WCDMA, TD-SCDMA, WiMAX, ISM, LTW cellular infrastructure and ultra-low noise systems.
These parts comprise of a single/multiple stage high linearity, high gain low noise GaAs pHEMT amplifier. They offer low thermal resistance for enhanced mean time between failures (MTBF). They are completely DC bypassed and are realized in various sizes and pin packages.
LNAs active bias circuitry internally provides stable performance over temperature and process variations. Each BOM also has an external resistor component to adjust the supply current and has been tested to operate over the temperature range of -40 to +85 ºC. A recommended range of bias comes with the application datasheet of the part. Operating the LNA anywhere between the specified bias will yield good performance. The LNAs have been tested for electro-static discharge (ESD) as well, which includes human body model (HBM), machine model (MM) and charged device model (CDM) testing.
Presented here is the quick summary of the design methodology for discrete and integrated LNA products. These LNA generate good gain, low NF, unconditional stability, and high linearity, all in a reasonably broad frequency range. For wireless infrastructure systems they form essential building blocks, and Skyworks’ datasheets and application notes make these products easily deployable.
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Skyworks Solutions, Inc.
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