Broadband Low-Loss Limiter MMICs
By Andy Dearn and Liam Devlin, Plextek RF Integration
Limiters are essential building blocks in receiver front-ends, where they are used to protect the low-noise amplification circuitry from damage by high power signals (such as nearby transmitters), which could otherwise result in permanent damage. Limiters need to be low loss, as any insertion loss adds directly to the noise figure of the receiver. In many applications, small size and weight and broadband operation are also desirable. This article describes PIN diode limiter MMIC designs that meet all of these requirements with an operating band of 0.5GHz to 20GHz.
PIN diodes are a popular technology choice for limiter circuits because a small device is able to handle relatively large amounts of power. They are available as discrete components that are frequently used to realize limiter modules. PIN diodes are also available on IC processes; this results in reduced circuit parasitics and facilitates the design of broadband, low-loss components. The limiter IC designs presented here use the commercially available Vertical PIN diode (VPIN) process from TriQuint.
A PIN diode takes its name from its structure: it comprises a region of high resistivity “Intrinsic” (I) material sandwiched between regions of P-type and N-type semiconductors, as depicted in Figure 1A. When the PIN diode is forward biased, charge carriers are injected into the I region, lowering its resistance. Thus, at RF and microwave frequencies, a PIN diode behaves as a current controlled resistor, and can therefore be configured to make excellent RF/microwave switches.
The electrical equivalent circuit for the intrinsic PIN diode is shown in Figure 1B. It includes a parasitic capacitance (Cj) in parallel with the junction resistance (Rj). The parasitic junction capacitance affects the high frequency behavior of the diode, and must be accounted for in the design process. The electrical model for a discrete, packaged PIN diode would also include package parasitics, which can be avoided by using an integrated design.
When configured as a limiter, PIN diodes are normally mounted in shunt to ground. When high power RF signals are present, charge carriers are injected into the I region of the diode on one half cycle and removed on the opposite polarity half cycle. Imperfections in the I region and statistical considerations mean an accumulation of charge develops in the I region, thereby reducing the diode’s resistance. This charge generation also results in a DC current (a rectified portion of the RF signal) which must have a DC return path in order for the limiter to function correctly.
Design and Simulation
The design methodology adopted with the limiters that are presented here was to use pairs of antipodal (back-to-back) shunt mounted diodes. This approach inherently includes a DC return and avoids the need for a broadband RF choke. The design approach used was to absorb the parasitic capacitance of the zero-biased back-to-back diode pairs into a low-pass filter structure. This allows the realization of a broadband design that covers the desired 0.5GHz to 20GHz operating band. Multiple stages of shunt diode pairs can be incorporated into the design, which provides limiting to slightly lower power levels than those achieved with just a single diode pair. The use of multiple shunt stages also provides a convenient stepping stone to increasing the power handling capability of the limiter.
A schematic of the basic limiter (which was based on a 5th order low-pass filter) is shown in Figure 2. The two pairs of back-to-back PIN diodes replace the shunt capacitors in the low-pass filter. High impedance (narrow) metal tracking is used to implement the series inductors of the filter. On-chip DC blocks (MIM capacitors) are included at both the RF input and output.
The small-signal simulated S- parameters of the basic symmetrical limiter are shown in Figure 3A. The results include practical bond-wire inductance at the input and output ports. All transmission line structures are EM simulated. Return loss is greater than 18dB above 2GHz, but degrades a little at low frequencies to 13dB at 500MHz. This is a result of the practical size limitations of the on-chip DC blocks. A similar design without on-chip DC blocks would be straightforward to implement, and would allow the limiter performance to be extended to lower frequencies.
When a high level RF signal is incident on the limiter, the effect is to turn on the diodes as the RF biases them into forward conduction. This effect can be understood by changing the small-signal model for the two front-end diodes from the zero-bias state to a +1.25V/5mA forward conduction state. The resulting attenuation is shown in the red trace of Figure 3B, and indicates that under large RF signal drive, the limiter should limit the signal breaking through by the order of 20 to 25dB. Simulations using large-signal PIN diode models provide an improved means of simulating the effect, and are presented later in this article.
Increasing Power Handling
The power handling capability of the limiter is set by the size (area) of the first diode pair. When an RF signal is present, forward current will flow in these diodes, and this will increase with increasing RF power. The current handling capability of the diodes—and hence the RF signal handling capability of the limiter—is set by their area. The symmetrical 5th order limiter described above should be able to withstand a CW input power in the region of 5W.
In order to increase the power handling capability of the limiter a second, asymmetrical topology was developed. This is shown in Figure 4. The main change is that each of the first antipodal pair of shunt diodes is replaced by a cascade of two diodes. These are set to be twice the area so that the two in cascade have twice the current handling capability and the limiter can handle 6dB more input power around 20W CW. While the larger area diodes have twice the capacitance, the use of two diodes in cascade means that overall effective capacitance is nominally unchanged, so the achievable RF performance should be very similar.
The small-signal simulated S-parameters of the high-power asymmetrical limiter are very similar to those for the symmetrical limiter, which were shown in Figure 3A with just a very slight degradation in return loss and a tiny increase in insertion loss.
Large-signal Modeling of the Limiters
Accurate large-signal modeling of PIN diodes is problematic, and the foundry does not provide large-signal models for the PIN diodes. However, Plextek RFI implemented a large-signal model based on the measured performance of previous limiter designs fabricated on the TriQuint VPIN process. The plots in Figure 5 show the simulated power transfer characteristics of the two limiters. The three traces show performance at 2GHz, 10GHz and 18GHz. It can be seen that the difference with frequency is relatively modest. The saturated output power level is around 17 to 18dBm.
It should be noted that practical limiters designed on this process have a more complex power transfer characteristic, with a pronounced “kink” where the output power falls back after reaching a peak, as shown in Figure 6. The large signal model does not predict this kink but it does predict the correct peak output power level.
The resulting limiter ICs are very compact, as shown in the layout plots of Figures 7A and 7B. Die area is identical for each IC at just 1.46 mm2.
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