JESD204B and its Impact on Overall Pipeline ADC Latency
By Thomas Neu, System Engineer, Texas Instruments
JESD204B is an industry-standard serial communications link that simplifies the digital data interface between data converters and other devices, such as FPGAs, DSPs and ASICs. The standard reduces routing between devices, slashing the input/output and board space requirements for applications, such as wireless communications, test and measurement, and defense and aerospace.
When selecting a high-speed analog-to-digital data converter (ADC), ADC latency often does not make the list of key design considerations and critical specifications. The new JESD204B high-speed serial interface is quickly gaining worldwide adoption and becoming the digital interface of choice. However, it also adds extra clock cycles to the ADC latency. Because of this, some system designers are holding on to the traditional lower latency interfaces. This article breaks down the main contributors to the latency of high-speed pipeline ADCs and explains why certain systems are trying to avoid the JESD204B interface.
While system designers usually specify the component latency in nanoseconds, the pipeline ADC latency is measured in clock cycles. It is commonly defined as the time duration when the input signal is captured by the ADC sampling clock until it is presented to the digital outputs (Figure 1). As the sampling rate increases, the absolute latency in nanoseconds for a given amount of clock cycles decreases.
The propagation delay (TPD) stands for the buffering delay on the clock input and on the output clock and data. Typically, it is not included in the latency number. It is dependent on the amount of buffers used and the delays of the individual buffers variance over process, voltage and temperature (PVT), which makes the propagation delay a variable element. The propagation delay can range typically from less than one to several clock cycles.
A pipeline ADC data sheet also specifies the aperture delay, which is not included in the latency number. The aperture delay is the time delay between when the rising edge of the input sampling clock arrives at the ADC and the actual time at which the sampling occurs.
Pipeline ADC Latency Break-down
The latency of a modern high-speed pipeline ADC is very design dependent. The ADC can be broken down into four basic building blocks: analog front-end, pipeline stages, digital block, and output stage (Figure 2). Since the actual implementation of each block is up to the ADC designer, it can vary from design to design as different tradeoffs of ADC sampling rate, power consumption, and AC performance are considered.
The analog front-end consists of the sample and hold amplifier, and sometimes an analog input buffer to help suppress the sampling glitches from the switch capacitor sampling circuit. This block typically consumes only half to one clock cycle.
The pipeline section consists of the individual pipeline stages and the error correction function which assembles the output data. Each pipeline stage consists of a low-resolution ADC and DAC, and residue amplifier. This usually takes half of a clock cycle as rising and falling clock edges are used between alternating stages. Naturally, the amount of stages required depends on what resolution is chosen for each stage, and the resolution doesn’t have to be the same for each stage. A higher resolution per stage reduces the overall pipeline latency, but also entails more design complexity because a larger amount of comparators (and thus more power consumption) with tighter matching and better offset are required. Therefore, depending on the number of stages, the pipeline section latency can range from approximately two to five cycles. The error correction can take an additional one to two clock cycles, depending on implementation.
The latency in the digital block is also heavily dependent on the amount of features included and on the chosen architecture. For most pipeline ADCs it ranges from approximately three to ten clock cycles. While the end user often appreciates features like digital gain control, DC offset correction or data formatting like 2s complement/offset binary or MSB/LSB first, this extra flexibility adds clock cycles to the ADC latency. Often these functions can be bypassed to improve latency, but even the muxes required add extra latency.
The ADC’s sampling rate itself can impact the latency negatively. As sampling rates increase, the digital block may need to operate at a slower speed due to process limitation or simply to save power consumption. For example, two samples may be processed simultaneously when operating the digital section at half-rate, resulting in the same effective ADC speed. But the paralleling and serializing operation still eat up additional clock cycles.
The output stage consists of the data formatter and digital interface. In the traditional LVDS interface, this block merely is a shift register that puts the digital data into the LVDS output buffers and consumes one or two clock cycles, depending on if single, double (DDR) or quad-rate (QDR) LVDS is implemented. Alternatively, the new JESD204B interface adds a bit more complexity to this block as it includes 8b/10b encoding, the data scrambler, and the serializer itself. As the ADC sampling rate and the serializer transmit data rate increase, more internal parallel processing may be required which, in turn, can negatively impact the latency.
Depending on the design, ADC sampling rate and implementation, the latency of the JESD204B interface can range from about four to as high as 20-30 clock cycles.
System Latency Considerations
While most system designers embrace the benefits of the JESD204B interface, such as the deterministic latency or the greatly simplified PCB routing, not all of them may be able to accommodate the additional latency that comes along with it. Certain applications such as control loops or electronic countermeasures demand an extremely short system roundtrip delay. As shown earlier, the JESD204B interface can add a significant amount of extra delay. In a real system this delay actually gets multiplied times four. In the receive path, the data first needs to be deserialized before it can be processed. The same is true on the transmit side, where the data first is serialized in the processor/FPGA, and then deserialized again inside the DAC.
Texas Instruments is cognizant of the fact that the JESD204B interface may not work for every application. Therefore, for the foreseeable future, the plan is to offer leading-edge, high-speed data converters with both the new JESD204B interface and a version with a traditional LVDS interface wherever possible. One such example is the new dual 16-bit 250 Msps ADC that is available with JESD204B (ADS42JB69) as well as a DDR/QDR LVDS (ADS42LB69) digital interface. The ADS42JB69 has a nominal latency of 23 clock cycles while the ADS42LB69 outputs data after just 14 clock cycles. With these two options, the system designers can choose between using the JESD204B interface for easier board design and the lower latency LVDS interface.
Download a datasheet for the ADS42JB69 at: www.ti.com/ads42jb69-ca
and the ADS42LB69 here: www.ti.com/ads42lb69-ca
For more information about this and other interface solutions, visit: www.ti.com/interface-ca.
About the Author
Thomas Neu is a systems engineer for TI’s high-speed data converters group, where he provides applications support. Thomas received his MSEE from Johns Hopkins University, Baltimore, Maryland. He can be reached at firstname.lastname@example.org.
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