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Addressing High-Performance RF/Microwave Circuit Design Challenges


As microwave products continue to improve their performance from one generation to the next, the tools that help engineers develop these products also continue to advance. This includes test instruments as well as software simulation. On the design front, several dominant design flows have emerged to serve specific needs. For MMIC and RF PCB circuit design, ADS from Keysight Technologies (formerly Agilent) and Microwave Office from National Instruments (formerly AWR Corp.) are two commonly used design environments used throughout the industry. When it comes to 3D structures such as antennas/arrays, cavity filters, and connectors, ANSYS HFSS is often considered the industry gold standard.
Circuit design flows include support for technology libraries (including electrical and layout models and process stack-up), design entry (schematic capture) user interface, simulation set-up, optimization and post-processing. Electromagnetic simulation of passive structures as a function of model development or for co-simulation with the transistor-level circuit analysis has become so commonplace that virtually all of the design flows above offer some form of EM technology to simulate S-parameter data from physical layout and process stack-up information. Given the impact of the passive design on overall circuit performance, many design groups require EM verification before fabrication sign-off. This article will discuss how new capabilities in HFSS enable it to be readily used by rank and file circuit designers within any mainstream MMIC, RFIC and PCB design flow to not only verify the final design but also to ensure the success of the overall design through optimization of passive structure/active device interaction using EM-centric circuit design.
Many circuit designers use the planar EM analysis capabilities integrated into their circuit design environments as a matter of speed and convenience. For problematic structures, company simulation experts are often called in by designers to use HFSS to model more complex structures and provide the designer with a set of S-parameters to embed back into their circuit simulation.
However, as technologies advance and frequencies push higher and performance requirements become more stringent (low loss, more efficiency/linearity, lower phase noise, etc.), designers increasingly need a better understanding of how structures and materials in their design impact overall performance. This insight is obtained through more rigorous EM analysis. With demanding product delivery schedules, companies relying on an EM expert for answers face a potential bottleneck. Recently, ADS and MWO have introduced 3-D finite element simulation capabilities into their design flow in order to address this growing need to analyze and optimize the electrical behavior of structures within the physical circuit design. While integrating 3-D FEM solvers into a circuit design environment is the direction tools are moving toward, the twenty plus years of simulation expertise built into the HFSS solver technology gives it a clear advantage in terms of speed and accuracy.

Insertion loss of two differential pairs vs. frequency
Figure 1: Insertion loss of two differential pairs vs. frequency

Fortunately, recent product developments make it easier for RF and microwave engineers to access HFSS accuracy for circuit design whether they use ADS or Microwave Office as their primary design flow or choose to address RF/mW circuit design or signal integrity analysis all within the HFSS design environment. More importantly, HFSS offers more rigorous EM simulation results, often with faster simulation run times than alternative solvers. The most recent product release offers three new key features to support the circuit designer characterizing structures with HFSS; these features include a 2-D layout editor to support predominantly planar design entry and manipulation in the HFSS modeler user interface, a new Phi mesher that provides 3-D EM accuracy more rapidly and a fully integrated linear, non-linear (transient and harmonic balance) circuit simulation for RF and SI design within HFSS. Together, these features allow circuit designers to move design data between platforms and take advantage of best-in-class tools without disrupting their existing design flows.

The Technology Behind the “Right Answer,” Now Tailored for MMIC/PCB Design
Simulating the “correct” electrical response of a structure is dependent on the proper meshing of the structure. For circuit designers without much experience in how to properly setup an EM simulation, a key benefit of HFSS is its automatic adaptive meshing, a highly robust volumetric meshing technique that includes a multi-threading capability that reduces the amount of memory used and results in faster simulation time. This proven technology eliminates the complexity of building and refining a finite element mesh and makes advanced numerical analysis practical for all levels of engineering skills. The user only needs to specify the structure geometry, material properties and the desired output. Without adaptive meshing, the user would almost need to know the solution in order to setup the mesh correctly for an accurate solution.
HFSS’s accuracy is also made possible through the use of tetrahedral mesh elements to determine a solution to a given electromagnetic problem. These mesh elements in combination with the adaptive mesh procedure create a geometrically conformal (surface accurate) and electromagnetically appropriate mesh for any arbitrary HFSS simulation. This ensures that HFSS will provide the highest fidelity result for any given simulation. In addition to creating standard first-order tetrahedral mesh, HFSS employs advanced techniques developed over many years to create an exceptionally efficient mesh and overall solution process. This fidelity is needed to provide greater dynamic range and characterization of high frequency losses that impact circuit performance, such as phase noise, efficiency/linearity and more.
The automatic adaptive mesh process is based on iterative mesh refinement, which identifies the region where the mesh needs to be refined to reduce the error between two solutions. For layered geometries such as PCBs, packages and ICs, the new phi mesher in HFSS provides extremely fast generation of an initial conformal tetrahedral mesh. These structures can often exhibit a high degree of geometric complexity associated with the numerous traces, vias, pads and solder balls or bumps. This complexity can result in initial mesh generation times approaching or even exceeding the total time for the electromagnetic simulation itself. Unlike traditional finite element meshing technologies that make no assumptions about a given geometry, the phi mesher takes advantage of knowledge regarding the stacked-up nature of these layered designs. The phi mesher decomposes the layers into a set of convex polygons from which 3-D convex polyhedrons are derived to fill the volume within the layers, which are then further processed into conformal tetrahedrons for the initial 3-D tetrahedral mesh.
This algorithm avoids the time-consuming creation and destruction swapping processes common in 3-D FEM meshing. All complex calculations are performed in 2-D instead of 3-D, providing further robustness and scalability to the algorithm. The end result is that for these types of complex layered structures, the phi mesher can reduce mesh times by a factor of 30 or more when compared to general purpose 3-D FEM meshing techniques, allowing HFSS to solve bigger problems or perform practical parametric optimization.

Return loss of two differential pairs vs. frequency. Accessibility for RF/mW circuit designers
Figure 2: Return loss of two differential pairs vs. frequency. Accessibility for RF/mW circuit designers

Simulation Results
To demonstrate the new phi mesher, a frequency sweep from 0 GHz to 40 GHz was run to extract the s-parameter model in the requested bandwidth. Post-processing allows automatic identification of differential pairs from a single-ended terminal. Results can be plotted as single-ended terminal or differential pairs. Various results are shown (Figure 1: insertion loss in dB; Figure 2: return loss in dB of the two differential pairs, receiver (RX) and transmitter (TX); Figure 11 isolation between RX and TX differential pairs). Depending on the specification, the designer will identify the frequency range of usage for the package on board device.
Leading concerns for any engineer considering the adoption of new technology include disruptions to existing product development processes and training*. As a result, engineers are often justified in their desire to work only with the design tools they are accustomed to and in many cases have customized to their specific needs, including the development of design kits and scripts. As we have seen with the emergence of GaN and RF CMOS, adopting new technologies is necessary to remain competitive. Fortunately, most circuit design operations (schematic entry, layout, simulation set-up, post-processing) are common to all design platforms and the intuitive user interface has become ubiquitous thanks to software vendors aligning their products to end users’ preferences. Standard circuit and layout design entry has now been integrated directly into HFSS to support the MMIC/package/PCB designers using it to provide electrical characterization data to ADS or Microwave Office or as a stand-alone circuit design tool.
To support a flow with layered structures and designs, HFSS now offers design entry based on a 3-D layout with associated stack-up definition from which a 3-D simulation structure is automatically created. This interface is similar to the one used by board and package designers in a classic EDA flow. To integrate with ADS, Microwave Office or any electrical CAD software, the full database design can be imported by reading the exported DXF or GDSII layout files from either tool. Stack-up libraries from specific foundry processes can be imported from an existing foundry technology file or recreated one time for each process using the stack-up layer graphical editor.
Alternatively, with the integration tool ALinks from ANSYS, third-party IC, PCB and electronic package layout files can be imported, edited and exported in a neutral file (ANF) format. The resulting ANF file is readily available for subsequent design and analysis within. All information, drawing primitives, nets, padstack, bond wire and stack-up definitions are translated in the 3-D layout interface. Moreover, maintaining drawing primitives allows definition of parameters, such as trace width, that would not be possible with simple polygons. Once imported, a part of the layout can be cut out by selecting nets of interest or specifying an area using a polygon. A complete board can be imported using a *.brd file, then a cut-out design can studied by selecting a few nets. Similarly, a full package can be imported using a*.mcm file, then a cut-out design can be created by selecting the nets of interest. Engineers can simulate the interactions between both package and board, easily working with circuit structures that do not have the same stack-up, which could be challenging if you want to combine the board and the package in one simulation. HFSS 3-D layout flow supports hierarchy, which allows a design to combine two designs that have different stack-ups with a simple copy/paste.
For HFSS 3-D layered geometries, the exporting of the stack-up, material properties, boundary conditions and port settings are all included when you click “export to HFSS” from within the MWO software. This means that any MWO project that includes bond wires and BGA balls can then call upon HFSS for further EM characterization of these entities. Support for automatic embedding of the resulting HFSS derived S-parameters is being developed as is expected to be available in the commercial release. This integration currently does not include support for arbitrary 3-D structures (ie, .SAT files).

Circuit Analysis within HFSS
ANSYS HFSS now supports an add-on “RF option” that offers harmonic balance circuit simulation for nonlinear microwave circuit analysis, filter synthesis as well as DC, transient, oscillator, load-pull and envelope circuit analysis capabilities. This option allows users to study the interactions between transistor-level, passive components (surface mount, IC and/or package embedded) with the structure defined and analyzed in HFSS. This allows circuit designers with a performance critical passive design, such a low phase noise oscillator, to optimize the passive design using a non-linear harmonic balance simulation that is fully integrated into a parametric HFSS analysis. Another use model would allow designers to troubleshoot problematic coupling in a densely populated (multi-layer) design by examining field strength across the structure with accurate signal levels, thanks to the inclusion of transistor/component models. With an optimized component, package or sub-circuit, the geometry and S-parameter data can be exported into other design flows for further product development steps if necessary.

The HFSS RF option includes:

Circuit analyses
Linear network analysis (included with HFSS)
DC analysis with multiple continuation options
Multi-tone harmonic
balance analysis
Shooting method option
Oscillator analysis
Autonomous plus driven sources option
Time varying noise and phase noise analyses
Envelope analysis
Multi-carrier modulation support
Load pull analysis and model support
Periodic transfer function analysis

As evident by the availability of EM simulation technologies within RF/microwave circuit design environments, electromagnetic analysis has widely been accepted as a necessary step to ensure successful product development. As frequencies, circuit densities and performance requirements continue to increase, the demand for solvers that offer higher fidelity (accuracy), speed and ability to solve larger problems will also increase. New capabilities in ANSYS HFSS address this demand for best-in-class solver technology and make it more accessible to the RF/microwave circuit designer regardless of which tools represent their primary design environment.