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Powering GSPS or RF Sampling ADCs : Switcher vs. LDO


by Umesh Jayamohan, High-Speed Converter Application Engineer

Analog Devices, Inc.


The Analog-Digital Converter (ADC) is an integral component in any system that depends on gathering information from the outside (analog) world for (digital) processing. These systems vary in applications from communications receivers to electronic test and measurement, to military and aerospace, to name a few. Advancements in silicon processing technology (65nm CMOS, 28nm CMOS, etc.) have enabled the high speed ADC to cross the GSPS (Giga Sample Per Second) barrier. What this provides the systems designer with is the ability to sample wider and wider bandwidths for digital processing. Systems designers are constantly trying to reduce overall power for environmental and cost reasons. Traditionally, low noise LDO (Low Drop Out) regulators have been recommended by ADC manufacturers for powering GSPS (or RF Sampling) ADCs in order to extract maximum performance. However, this is not an efficient Power Delivery Network (PDN) implementation. Systems designers are increasingly demanding to use switching power regulators to power the GSPS ADC directly without a significant drop in ADC performance.

The solution lies in careful PDN implementation and layout to ensure that the ADC performance is not compromised. This article discusses the difference between linear and switching supplies and demonstrates that combining a GSPS ADC with a DC-DC converter can significantly improve system power efficiency without any penalty in ADC performance. This article discusses the performance of the GSPS ADC using a combination of power delivery networks and makes comparative analyses on cost and performance.

Traditionally Recommended PDN for GSPS ADC

A high bandwidth high sample rate ADC (or GSPS ADC) can have multiple power domains (AVDD, DVDD, etc.). With the shrinking geometries, not only have the power domains increased in number, but also the number of different voltages required to power the ADC have increased as well. For example, the AD9250 [1], a 14-bit 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter, is built using the 180nm CMOS process and has three domains (AVDD, DVDD and DRVDD). However, all three domains are the same voltage: 1.8V.

Now consider the AD9680 [2], a 14-bit 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter, which is built on a 65nm CMOS process. This GSPS ADC has seven different domains (AVDD1, AVDD1_SR, AVDD2, AVDD3, DVDD, DRVDD and SPIVDD) and three different voltages: 1.25V, 2.5V and 3.3V.

The proliferation of these supply domains and the various voltages is somewhat of a necessity for operation at these sample rates. They are required to ensure proper isolation between the various circuit domains (sample, clock, digital, serializer, etc.) while providing optimal performance. It is for this very reason that the ADC manufacturers design the evaluation boards and recommend an elaborate power supply design to ensure minimal risk and maximum performance. For example, Figure 1 shows the block diagram representation of the default PDN used in the AD9680 evaluation board. The power input is derived from the 12V/1A and 3.3V/3A supplies offered by the FMC (FPGA Mezzanine Connector) using Vita57.1 specification. The ADP2384 [3] and ADP2164 [4] DC-DC converters were used to step down the voltages to a manageable level so the LDOs can regulate without having to go into thermal shutdown.

Figure 1 : Default PDN for the AD9680 Evaluation Board
Figure 1 : Default PDN for the AD9680 Evaluation Board
Figure 2 : Simplified PDN for the AD9680 Evaluation Board
Figure 2 : Simplified PDN for the AD9680 Evaluation Board

It does not take much to realize that this is an expensive implementation, with seven LDO regulators, one for each domain. This PDN may be the most optimal in terms of performance, but it certainly is not the most cost effective or efficient in terms of cost of operation. Systems designers find it challenging to implement a system with multiple ADCs. For example, a phased array radar implementation will contain 100s of AD9680s, all working synchronously. It is unreasonable to ask the systems designer to have one LDO regulator per voltage domain across 100s of ADCs.

A Simpler PDN for GSPS ADC

A more cost effective approach to the PDN design would be to combine the domains that have the same voltage value (say all 1.25V Analog domains) and drive them from the same LDO. This reduces the component count (and Bill of Material — BOM — cost) and may be suitable for some designs. The simplified PDN is shown in Figure 2 as implemented on the AD9680 evaluation board. In this implementation, the entire AD9680 can be powered using a single 3.3V input.

 DC – DC Converter Driving the AD9680

A further simplification to the PDN can be implemented by removing the LDO that supplies the 1.25V domains altogether. This would be the most efficient and cost effective solution. The challenge here is to ensure stable operation to the DC–DC converter so as to not affect the ADC’s performance. The PDN where the ADP2164 drives all the 1.25V domains (AVDD1, AVDD1_SR, DVDD and DRVDD) of the AD9680 is shown in Figure 3.

Comparing the Various PDNs

The three PDNs discussed above were put to test along with a fourth network where the AD9680 evaluation board was powered from the bench supplies. Table 1 lists the various Power Delivery Networks implemented on the AD9680 evaluation board.

Since SPIVDD could support 1.8 – 3.3V and was considered a non-critical node, it was powered using a 1.8V LDO output. In a regular system implementation, the SPIVDD can be connected to the 2.5V or 3.3V domain. That said, the SPIVDD connection should still be monitored in systems where the SPI bus is shared between many ADCs and DACs. If this is the case, care must be taken to ensure that the normal SPI operation does not cause supply transients on the SPIVDD domain. This might trigger a Power On Reset (POR) situation if the SPIVDD goes lower than the threshold level.

Table 2 and Table 3 show the SNR and SFDR performance, respectively, of the AD9680 when using the various PDNs. The recommendations for front end network and register settings for various Nyquist zones were followed as per the AD9680 datasheet [2].

Figure 3 : Using DC–DC Converter to power the AD9680
Figure 3 : Using DC–DC Converter to power the AD9680

The PDN using just the DC–DC converter to power the AD9680’s 1.25V domains (PDN #3) shows good performance over the input frequencies. This proves that it is possible to combine domains and power them efficiently and cost effectively without paying a huge penalty in ADC performance. The PDN supplied from the bench provides the best noise performance as it is the lowest noise power source. However, it is worth noting that the PDN #3 consistently shows better SNR performance than the default network (PDN #1). This could be attributed to the fact that LDOs are good for low frequency clean up but do not do much above a few 100KHz even when they are in the circuit. This could explain the 0.2dB advantage in SNR when using the PDN #3.

FFT Plots

Figure 4 and Figure 5 show the single tone FFTs at 170MHz and 785MHz input, respectively. The FFT shows no spectral degradation due to the fact that the 1.25V domains have been powered from a single DC–DC converter.

Switching Spurs

In addition to the noise performance, the DC–DC converter implementation should also be checked for spurious content due to the switching elements and the magnetics involved. This is where careful layout techniques to reduce ground loops and ground bounce will be beneficial. There are many resources that can help with measurement of the switching supply noise [5], [6]. The sideband spurs appear on either side of the fundamental offset by the switching frequency (in this example, 1.2MHz). It must be noted that the output filter stage shown in Figure 2 or Figure 3 is a two-stage filter. This two-stage filter is a main contributor in reducing the switching noise (ripple) that helps improve the ADC noise (SNR) performance. By the same token, the two-stage filter also helps in reducing the switching spurs that manifest itself in the output FFT. These are shown in Figure 6 and Figure 7 for 170MHz and 785MHz, respectively.

The level of the sideband spur can be estimated by understanding the PSRR (Power Supply Rejection Ratio) or the ADC’s power supply domain [7].

Figure 4 : Single Tone FFT at 170MHz input, with PDN #3
Figure 4 : Single Tone FFT at 170MHz input, with PDN #3
Figure 5 : Single Tone FFT at 785MHz input, with PDN #3
Figure 5 : Single Tone FFT at 785MHz input, with PDN #3
Figure 6 : 1.2MHz side-band switching spur at 170MHz input. Spur level = -105dBFS
Figure 6 : 1.2MHz side-band switching spur at 170MHz input. Spur level = -105dBFS
Figure 7 : 1.2MHz side-band switching spur at 785MHz input. Spur level = -94dBFS
Figure 7 : 1.2MHz side-band switching spur at 785MHz input. Spur level = -94dBFS

Simulating DC–DC Converter Switching Circuits

The two-stage filter at the output of the DC–DC converter can be simulated using a tool such as ADIsimPE [8]. Figure 8 shows the ADIsimPE schematic generated to simulate the output noise and stability characteristics of the PDN. ADIsimPE is a convenient and powerful tool that helps the systems engineer design, optimize and analyze power supply networks.

Figure 9 shows the output ripple at the output of the first stage and the filtered output after the second stage of the circuit, simulated in ADIsimPE. The ripple as shown here is around 3mVpp.

Bill of Material

Table 5 shows the Bill of Material used for the simplified PDN of the AD9680 evaluation board which is shown in Figure 2. By using the network shown in Figure 3, a systems designer can realize savings of up to 40 –45% in BOM cost. The BOM cost is estimated by calculating the 1k unit prices of the components on a popular electronic component vendor website.

PDN Efficiency Estimates

Table 2 lists the efficiency estimates of the Power Delivery Networks implemented on the AD9680 evaluation board.  With a 3.3V input, the switching regulator provides a 13% improvement in efficiency with a savings of almost 730mW. This number can be improved if the 2.5V domain is also generated using a switching supply. In this example, the LDO is translating the 3.3V input to the 2.5V output, which hurts overall PDN efficiency. This translation causes the LDO to operate at 75% efficiency. The savings shown here is for a single converter and would be amplified dramatically in systems utilizing multiple ADCs.

Component Selection and Layout

The performance of the ADC when running on the various PDNs depends on not only careful design, but also on the selection of components and their layout on the PCB. The high currents produced in a switching power supply often lead to strong magnetic fields that can couple into other magnetic components on the board, including inductors found in matching networks and transformers used to couple analog and clock signals. Careful board layout techniques must be utilized to prevent these fields from coupling into critical signals.

Inductor Selection

Since the inductor and the capacitor that form the output filter stage perform the bulk of the power delivery, they need to be selected carefully. In this example, a mix of shielded and unshielded inductors were used. The first filter stage used a shielded inductor. The second stage could do with an unshielded inductor in this case. However, it is recommended to use shielded inductors in both stages to minimize possible EMI emissions. The inductors also were chosen to have enough headroom in terms of saturation current (ISAT) and DC Resistance (DCR) to make sure they didn’t go into saturation or cause too much voltage drop across themselves.

Capacitor Selection

X5R or X7R capacitors are recommended for use as output filter capacitors. The capacitors also have to have low ESR (Equivalent Series Resistance). The low ESR helps in reducing switching ripple at the output. Another trick that is employed to minimize the total ESR and ESL (Equivalent Series Inductance) is to combine capacitors in parallel. As shown in Figure 3 and Table 5, the first filter stage uses 2x 22uF capacitors, whereas the second filter stage uses 4x 22uF capacitors. The voltage rating of the capacitors is also an important factor in its selection. This is because the dielectric of the ceramic capacitor degrades as the DC bias increases. This means that a 6.3V rated 22uF capacitor could degrade by up to 50% at a 4V DC bias [9], [10]. In this example, the 6.3V rated capacitor is used for the 1.25V supplies. Adding more capacitors at the output does increase the BOM cost and board space slightly, but this is good insurance against switching noise and ripple that could interfere with ADC performance.

Figure 8 : ADIsimPE schematic of ADP2164 driving the 1.25V domains
Figure 8 : ADIsimPE schematic of ADP2164 driving the 1.25V domains
Figure 9 : Stage 1 and Stage 2 outputs of the ADIsimPE simulation
Figure 9 : Stage 1 and Stage 2 outputs of the ADIsimPE simulation
Table 1
Table 1
Table 2
Table 2
Table 3
Table 3
Table 4
Table 4
Table 5
Table 5

Ferrite Bead Selection

As shown in Figure 3, ferrite beads are used to isolate the various domains. The selection of ferrite bead is also critical, as a higher than desired DCR (DC Resistance) of the ferrite bead will cause lower than optimal voltage at the domains. This low voltage results in less than optimal ADC performance (SNR and SFDR). Sufficient attention must be paid to the impedance characteristics, maximum DC current carrying capability and the DCR of the ferrite bead [11].

PCB Layout Considerations

In order to minimize the interactions between the switching regulator and the ADC, the DC–DC converter and its switching elements should be placed far away from any magnetics that interact with the ADC (front end matching network, clock network, etc.). Within the DC–DC converter layout, the two stage filter should be placed as close to the DC–DC converter as possible so as to minimize loop currents.


RF Sampling (or GSPS) ADCs offer a unique advantage in systems design in allowing digitization of wide swaths of bandwidth. The industry is keen on reducing the complexity, size and cost of power supply designs for these GSPS ADCs. It is possible to have a low noise and cost effective PDN that can power a GSPS ADC by paying adequate attention to the design, component selection and PCN layout. Thus implemented, switching regulators also help improve power system efficiency and provide operational cost and BOM savings, without any penalty in performance.


The author would like to acknowledge Justin Correll for help with the measurement and data collection.


[1] “AD9250,” Analog Devices, Inc., [Online]. Available: www.analog.com/ad9250.

[2] “AD9680,” Analog Devices, Inc., [Online]. Available: www.analog.com/ad9680.

[3] “ADP2384,” Analog Devices, Inc., [Online]. Available: www.analog.com/adp2384.

[4] “ADP2164,” [Online]. Available: www.analog.com/adp2164.

[5] A. S. Limjoco, “Understanding Switching Regulator Output Artifacts Expedites Power Supply Design,” Analog Dialogue, pp. 48-3, August 2014.

[6] Ericsson, July 2010. [Online]. Available: http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146097.

[7] R. Reeder, “Designing Power Supplies for High Speed ADC,” February 2012. [Online]. Available: http://www.analog.com/media/en/technical-documentation/technical-articles/MS-2210.pdf.

[8] “ADIsimPE,” [Online]. Available: http://www.analog.com/adisimpe.

[9] “GRM21BR60J226ME39L,” Murata, [Online]. Available: http://psearch.en.murata.com/capacitor/product/GRM21BR60J226ME39%23.html.

[10] I. Novak, K. B. Williams, J. R. Miller, G. Blando and N. Shannon, “DC and AC Bias Dependence of Capacitors,” in DesignCon, Santa Clara, 2011.

[11] J. Eco and A. Limjoco, “Ferrite Bead Demystified – Analog Devices Application Note 1368,” Analog Devices Inc., 2015.

Umesh Jayamohan is an applications engineer with Analog Devices (ADI) in the High Speed Converter Group (Greensboro, NC). He has been a part of Analog Devices since 2010. Umesh received his B.S.E.E. from University of Kerala, India, in 1998 and his M.S.E.E. from Arizona State University in 2002. Umesh is a member of ADI’s EngineerZone in the High-Speed ADC Support Community at https://ez.analog.com/community/data_converters/high-speed_adcs. Feel free to connect with me, UmeshJ, on EngineerZone at https://ez.analog.com/people/UmeshJ. Sign up on EngineerZone for free at http://ez.analog.com/welcome.