by Kevin Anderson, Qorvo Infrastructure and Defense Products
The development and implementation of RF component packaging technology is facing pressure on several fronts. These include ever-increasing demands for reduced size, weight, power, and cost (SWaP-C), and requirements for higher operating frequency, radiated power, and efficiency in power delivery and thermal management. In addition, recent U.S. Defense-based initiatives aim to onshore critical manufacturing technologies to address secure supply chain and strategic concerns. In response, stakeholders spanning government agencies and labs, academia and industry are investing in 2D/3D technologies to address these challenges and simplify the integration of RF with mixed-signal and digital functions. Combined with megatrend technologies pioneered for digital applications—and, separately, high-volume, mobile phone, front-end modules—RF System-in-Package (SiP) technology is poised to enter an exciting period of innovation and growth that is enabling next-generation, heterogeneous integration platforms.
The solution space for traditional microwave packaging is rich and highly diversified. For defense applications, there are typically two extremes in practice. One centers on component packaging (typically single die) with integration occurring at the printed circuit board (PCB) level; the other accomplishes integration through chip-and-wire assemblies that use highly customized hermetic packages. Over the past several years, the latter has proven unaffordable for use in many modern systems, both in terms of non-recurring investment as well as unit cost. Instead, incorporation of mature, low-cost, PCB-based solutions has emerged as the preferred choice in design and manufacturing for a wide variety of applications. In recent years, the power of 2D heterogeneous integration using organic interposers (also called laminates or laminate substrates) with wire bondable die has been harnessed, greatly simplifying system design, improving manufacturing yield and shrinking size. The example in Figure 1 shows a Ku-band downconverter module that measures 7.5 x 8.5 x 2.13 mm and integrates four die and multiple passives onto a surface-mountable organic interposer assembly. This class of air cavity assembly supports operation through 40 GHz with low associated RF routing losses and minimal degradation of MMIC performance. Use of overmold lowers the cost even further, as well as enhancing environmental robustness with operating frequencies through 30 GHz. Both are available with integrated copper heat sinks that enable GaN amplifier power dissipation up to 10 W when mounted onto a coined PCB. The size of the chips used is often dictated by the use of MMICs with full on-chip matching, with die area extending up to 30 mm2.
Commercial RF packaging has evolved dramatically over the past several years, with heterogeneous integration being fully exploited to provide compact solutions with complex front-end architectures that combine multiple technologies (for example GaAs, Silicon, and SAW/BAW die with passives). These 2D RF SiP assemblies use organic interposers as the integrating substrate. Die count is often two dozen or higher, and these are typically flip-chip attached to the interposer using copper pillar or solder ball bumping. Individual die size for this class of product is modest—typically < 4 mm2—sufficient for use of low-cost, off-chip matching at frequencies below 6 GHz, and dissipated power < 3W peak. Electromagnetic Interference (EMI) shielding is included to minimize unwanted RF coupling to other structures, and overmold encapsulation is used to provide environmental robustness and manufacturing handling ease. Figure 2 shows an example of a high-volume, 2D RF SiP product for mobile applications that measures 6.5 x 8.6 x 0.8 mm.
Advanced packaging of commercial digital products early in the 21st century is widely touted as the vehicle that will enable semiconductor solutions that extend the industry’s multi-decade march toward fulfilling Moore’s Law. Among the numerous state-of-the-art (SOTA) innovations is a megatrend toward the use of heterogeneous integration, largely targeting applications that combine Graphics Processor Unit (GPU) die with High Bandwidth Memory (HBM) die or chip stacks (i.e. 3D “memory cubes”) to minimize size, interconnect trace length (for increased bandwidth) and cost. One example among many is the rise in the use of Fan Out Wafer Level Packaging (FOWLP); in this case, integrating four die within a digital SiP that measures 10 x 10 mm .
U.S. government funding has played a major role in, first, recognizing the strategic need to develop revolutionary materials, devices, and integration techniques to meet the requirements of advanced systems, and second, funding key programs to seed multiple technologies to help fulfill the vision . DARPA has sponsored a series of these programs, including Compound Semiconductor Materials on Silicon (COSMOS), Diverse Accessible Heterogeneous Integration (DAHI) and Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS). The goal of DARPA Multi-Beam Digital Arrays at Millimeter Wave (MIDAS, see Figure 3), currently underway, is to create the digital array technology that will enable next-generation Department of Defense (DoD) millimeter wave systems . An NSWC Crane-sponsored program, State-of-the-art Heterogeneous Integration Packaging (SHIP), is targeting demonstration of a novel approach to a secure, assessable, and cost-effective SOTA-integrated, design, assembly and test. Leveraging the expertise of commercial industry, SHIP is expected to fund four-year Phase 2 programs addressing both RF and digital prototype capabilities in 2020 .
Compound semiconductor (CS) technologies are used in a wide variety of performance-driven RF applications where lower cost silicon falls short. Prominent device technologies include Gallium Nitride (GaN), Gallium Arsenide (GaAs) and Indium Phosphide (InP), and circuit functions that span high-power and low-noise amplifiers, switches and other front-end sockets.
Traditional wire-bondable CS MMICs, however, typically incorporate distributed matching networks onto wafers thinned to 50 to 100 µm with backside plating and multiple grounded Through Semiconductor Vias (TSVs). As such, these MMICs do not lend themselves well to the type of heterogeneous integration used in silicon-based packaging solutions. Conventional silicon bumping is performed on un-thinned wafers with no backside features; grinding to final thickness is performed post-bump. In recent years, copper pillar (CuP) bumping of thinned CS wafers in volume has emerged as a key enabling technology to address this challenge. Qorvo has developed and released a domestic process for bumping with CuP and tin cap solder for thinned GaN and GaAs pHEMT wafers with backside vias and TSVs (see Figure 4). Importantly, this technology draws from the same CuP bump technology that is used for GaAs HBT and BAW die in high-volume manufacturing supporting commercial 2D RF SiP packaging. This enables flip-chip assembly of otherwise traditional MMIC die together with mainstream, traditional silicon die flip-chip attach, therefore paving the way for cointegration of CS and silicon die within the same SiP. In May 2020, Qorvo announced an award of a DoD contract to advance Copper-Pillar-on-GaN technology, with the goal to establish a high-yield, reliable copper flip-chip GaN MMIC technology and achieve Manufacturing Readiness Level 9 by 2022.
A second area which has already seen great traction in the market is Antenna-in-Package (AiP) technology . By incorporating an antenna (or multiple antennas) into the package, a highly compact RF SiP with built-in radiator capability is possible (see Figure 5). Beyond size reduction, this feature increases EiRP (or reduces prime power) by minimizing the loss traditionally incurred in passing the RF transmit/receive signals from the front-end components to the radiator. This technique is especially compelling at millimeterWave frequencies in which the antenna elements are physically small (typically less than 5 x 5 mm area), and it is in use today across multiple markets, including 5G millimeterWave front-end modules for handsets.
The confluence and harmonization of these many factors is now making it possible to create next-generation RF SiP solutions to meet increasingly demanding wireless system needs. These solutions will provide a rich trade space to enable optimal SWaP-C tradeoffs applicable to multiple markets, including defense and 5G infrastructure. As availability of CS copper pillar bumping expands, multi-chip architectures will emerge that span from the simple to the very complex. One embodiment, as an example, is a miniaturized transmit/receive RF SiP that integrates a GaN high-power amplifier MMIC with an LNA die (pHEMT or InP) and a GaN or silicon-on-insulator (SOI) switch die onto a common organic interposer. And on the other extreme, a digital transceiver SiP can be realized that combines flip-chip, RF front-end die with a data converter and an ASIC processor die using a silicon interposer as the integrating medium. Between these levels of integration resides a rich trade space that can be used, for instance, to develop a single RF SiP with multiple channels to shrink footprint, simplify next-level manufacturing complexity and improve PCB assembly yield.
Importantly, heterogeneous integration will empower system architects to better optimize implementation choices between the SiP and PCB realms when pursuing insertion of SOTA technology. This emerging RF SiP capability is especially attractive for use in tiled phased arrays operating at millimeterWave frequencies. However, these same advanced capabilities will also be used to improve SWaP-C tradeoffs for slat arrays and/or systems that operate at Ku-band frequencies and below. Combined with current and planned agency-funded initiatives, the ability to cost effectively manufacture these RF SiP solutions domestically will address the strategic requirements of the U.S. government.
RF SiP technology using heterogeneous integration with die pulled from multiple device technology nodes is poised to enter an exciting period of innovation and growth to enable next-generation RF sensor and transceiver solutions with domestic manufacturing. This capability will provide system designers with an enhanced capability to architect solutions that best optimize tradeoffs to minimize size and cost while pushing performance improvements—all afforded by selection and use of SOTA technologies only where needed.
About the Author
Kevin Anderson is Director of Integration Technology Research within Infrastructure and Defense Products at Qorvo. He is an industry veteran in RF technology development, with contributions spanning the disciplines of packaging, electrical and mechanical design, strategic marketing, and product line management. He received his BSEE and MSEE degrees from the University of Illinois Urbana-Champaign.
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