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AWR Design Environment V15: Design and Verification for 5G and Beyond


by Cadence

RF and microwave devices will be integrated into an unprecedented number of connected smart devices and systems enabled by the latest wireless technologies. Developing these systems requires a significant advance in multi-domain analyses, simulation capacity, design automation and seamless interoperability between RF/microwave EDA and the broader portfolio of mixed-signal integrated circuit (IC), printed circuit board (PCB), system-in-package (SiP), and system-on-chip (SoC) design tools. These tightly stacked components behave as mechanical systems with sophisticated electronics, transporting RF and high-speed signals through a complex network of interconnects. To function properly, mixed-technology systems require co-design and co-optimization across multiple domains of RF, analog, and digital simulation, aided by large-scale electromagnetic (EM) and thermal analysis, with robust design verification and signoff. 

The V15 Advantage 

Version 15 (V15) of the Cadence® AWR Design Environment® platform offers new and enhanced technologies that provide greater design efficiency and first-pass success to engineering teams developing or integrating III-V ICs, multi-technology modules, and PCB assemblies for 5G, automotive, and aerospace/defense applications (Figure 1).

Figure 1: AWR Design Environment RF/microwave design platform

Engineering productivity is improved with new analyses, faster and higher-capacity simulation technologies, time-saving design automation, and 5G New Radio (NR) compliant testbenches that support power amplifier (PA) and antenna/array design, EM modeling, and RF/microwave integration across heterogenous technologies. Figure 2 provides highlights of the new capabilities within this latest release.

Figure 2: AWR Design Environment V15 highlights

Design Environment and Automation

New design environment and automation features in AWR® V15 software help individual engineers and engineering teams be more efficient in their design entry, data display, and project management. Designers can adjust optimization goals directly from response plots, route design rule-compliant intelligent nets (iNets) in real-time, import Gerber-based layout designs into AWR Design Environment software for EM analysis, and provide more user capabilities for the design task at hand. 

Addressing the increasing size and complexity of RF/mixed-signal electronic systems, the new, faster layout and 3D viewer rendering capability in V15 enables users to zoom in and out and rotate large structures to inspect the physical design from any and all angles without any lag time. Large boards imported as IPC-2581 or ODB++ files from Cadence Allegro® PCB Designer or other layout tools can be readily inspected visually before editing and preparation for EM analysis using the PCB editing wizard.

EM Simulation Enhancements

Earlier this year, Cadence expanded its software solutions to better support RF integration within system-on-chip (SoC) and system-package (SiP) designs through the acquisitions of key enabling technologies, including AWR and its portfolio of RF and EM design tools, as well as Integrand’s EMX® software for analysis/extraction of large integrated circuits (ICs) and advanced packages. The Cadence Clarity® 3D EM simulation software tool addresses larger and more complex structures such as critical interconnects for PCBs, IC packages, and system on IC (SoIC) designs. Together, these products enable broader system design, from software down to the physical chip design. 

To enhance the speed and capacity of EM analysis for IC, package, and board structures, the Cadence AWR AXIEM® meshing and solver technologies have undergone several key improvements, resulting in improved mesh quality for faster simulation run times and the ability to solve larger problems with a reduced mesh. The latest enhancements to the AXIEM simulator in V15.01 can now detect and remove problematic mesh facets automatically with robust healing of high aspect ratio facets (HARF), optimized for thin layered MMI/RFIC designs (Figure 3).

Figure 3: Improved meshing and EM solver tackle large structures faster

Both large PCBs and SoC components can contain manufacturing features that do not impact RF performance, but can slow down EM analysis by increasing the problem size. In AWR Design Environment V15, shape pre-processing rules have been expanded to better address Si processes (handle large number of metal layers) and merge via arrays on user-specified layers and inside/ outside a specified region. In addition, enhancements to the AWR AXIEM DC solver (used for characterizing low-frequency behavior, such as bias networks) employ new sparse symmetric matrix technology, resulting in a 10- to 100-fold savings in time and memory usage.

Integrating EM Technology Into an RF/Microwave Design Flow

5G networks and devices support greater connectivity by relying on spectrally efficient modulation techniques, millimeter-Wave (mmWave) spectrum and multiple-in multiple-out (MIMO) antenna technologies. As a result, RF front-end architectures have become considerably more complex. The electronics used in today’s communication systems are physically realized through highly integrated, heterogenous multi-chip, multi-fabric modules. With expansive RF front-end content competing for real estate among high-speed digital, mixed-signal and power electronics, the need for high-capacity EM analysis is more critical than ever before to ensure design success.

Now that AWR is part of Cadence, accessing additional EM tools like Cadence Clarity is possible. The EM Socket tool was first introduced by AWR in 2003 and the EM Socket II architecture was enhanced in the 2013 V13 release. This revolutionary technology enables interoperability between third-party EM simulation tools and the company’s flagship high-frequency circuit design software, Microwave Office, enabling designers to choose the best tool for the job at hand. EM Socket software continues to be a vital part of the AWR Design Environment by allowing designers working in Microwave Office software to access the abilities of the Clarity EM simulator.

For RF designers that need high-capacity EM analysis today, the AWR Design Environment layout editor supports CAD export file formats such as DXF or GDSII for planar EM structures or ACIS for arbitrary 3D shapes. These file formats can be imported by the Clarity 3D solver to define the geometry of the EM structure for analysis. 

PA Simulation and Design Support 

AWR V15 software allows designers to optimize PA linearity performance through video band load-pull analysis of PAs operating under two-tone excitations. Designers can plot intermodulation (IMD) and third-order intercept point (IP3) results as a function of (F2-F1) impedance, directly investigating IMD products over swept input power. Load-pull analysis also supports impedance tuning at the 4th and 5th harmonics as well as the ability to generate contours on rectangular plots for enhanced visualization of performance versus load impedance (Figure 4). 

Figure 4: Video-band load pull supports low-frequency impedance optimization to reduce IMD product (left) and loop gain envelope provides fast and rigorous nonlinear stability analysis and optimization (right)

Synthesis Accelerates RF Designs 

The characteristic impedance and electrical length (delay) of transmission lines represent two important design parameters used to control the frequency-dependent circuit response of passive RF/microwave circuits. Using AWR V15 software, designers can now directly synthesize the physical attributes (width, length) of microstrip, stripline, or coplanar waveguide structures for a given substrate based on the desired electrical characteristics. 

Likewise, the electrical characteristics can be calculated directly from the physical properties of the single or edge-coupled transmission line placed in the schematic. Synthesis of circuit model parameters provides vital data for generating accurate layout of these transmission lines without having to invoke the transmission line calculator and manually transfer the results into the transmission line property dialog box. 

5G NR Library and DPD Models

The 5G New Radio (NR) library offers easy-to-configure signal sources and receivers that can be used to evaluate RF components and/or RF links using system-level measurements (Figure 5). New testbenches accelerate the component design and evaluation process with preconfigured 5G NR transmit (TX) and receive (RX) blocks and measurements supporting TX/RX functionality for both downlink and uplink. 

Figure 5: 5G NR libraries and test models for TX/RX device and RF link validation


AWR Design Environment V15 software brings new and enhanced RF/microwave design and simulation to the Cadence portfolio of EDA solutions. Advanced design automation optimizes engineering throughput and productivity by reducing manual design tasks and supporting tool interoperability. 

Robust simulation engines solve large structures more quickly using EM analysis with enhanced meshing and smart geometry handling for chip, package, and board characterization. Preconfigured, 5G NR-compliant testbenches provide signal sources and measurements for PA and RF link validation.

New circuit simulation capabilities address fast and rigorous nonlinear stability analysis for multi-stage and balanced amplifiers, and video-band load pull to optimize low-frequency impedance terminations for reduced intermodulation distortion. 

Network synthesis supports impedance network development using vendor components and process design kits (PDKs), and a new integrated transmission-line calculator and synthesis capabilities launched directly from schematic. 

Readers can learn more about AWR V15 at Cadence.com/go/awr/new.