5G NR Design for eMBB
by Cadence
Introduction
Enhanced mobile broadband (eMBB) extends the current mobile experience with high data throughput on the order of more than 10Gbps, high system capacity on the order of more than 1000X that of LTE, and a 3-4x improvement in spectral efficiency over 4G. This article examines some of the design challenges for eMBB and presents several case studies in which the Cadence® AWR Design Environment® platform was used to develop eMBB products for the third wave of communications, including high-speed mobile broadband and virtual reality, augmented reality, gaming, and much more.
The Third Wave of Wireless Communications
Each new generation of wireless technology has progressed exponentially, driving new services and business opportunities. This evolution is making possible a third wave of communications through 5G and future 6G technology, which will support new services for industry and society well into the 2030s and beyond. The next wave of communications focuses on the three areas of service (shown in Figure 1): enhanced Mobile Broadband (eMBB), Ultra-Reliable Low-Latency (URLLC), and Massive Machine-Type Communications (mMTC).
5G represents the first step towards this next wave of services with expanded connectivity and a significant upgrade in multi-media capabilities combined with artificial intelligence (AI) and the Internet of Things (IoT). 5G will be the first generation of mobile communications to utilize millimeterWave (mmWave) band frequencies, supporting bandwidths of several hundred megahertz (MHz), which will actualize ultra-high-speed wireless data communications of many gigabits per second.
In achieving this level of performance, 5G and subsequent systems will close the gap between the physical and cyber worlds. Today, mobile consumers use wireless connectivity to access the web from almost any location. In the future, high-speed coverage will be more widespread and faster, and there will be greater emphasis on uplinking information from real-world events and human and/or internet of things (IoT) activity to the internet.
Once this information is in the cloud, Artificial Intelligence (AI) can reproduce the real world in cyberspace and emulate it beyond physical, economical, and time constraints, so that “future prediction” and “new knowledge” can be discovered and shared. The role of wireless communications in this cyber-physical fusion is assumed to include high-capacity and low-latency transmission of real-world images and sensing information, and feedback to the real world through high-reliability and low-latency control signaling.
EMBB Background
EMBB extends the current mobile experience with high data throughput on the order of more than 10Gbps, high system capacity on the order of more than 1000 times that of LTE, and a much better spectral efficiency than LTE (3-4 times that of LTE).
The 3.4 GHz-4.2 GHz frequency range, also referred to as C-band, will aid the transition from 4G to 5G by providing access to a range of frequencies with less challenging propagation conditions and loss than occurs at mmWave. C-band supports transmission in a Non-Line-Of-Sight (NLOS) environment, facilitating indoor penetration on par with lower frequency bands. Compared to mmWave, the benefits of C-band are both economic and technical:
- Overlaying C-band on top of existing macro-cellular or small-cell grids eliminates the need for new cell sites, unlike those required for mmWave
- Access to a range of spectrum with fewer challenging propagation conditions than mmWave
- This approach reinforces transmission in a NLOS environment and facilitates indoor penetration on a scale like lower frequency bands
C-band also uses Time-Division-Duplex LTE technology (TDD-LTE), allowing transmission and reception on the same channel, compared to Frequency-Division-Duplex LTE (FDD-LTE), which uses paired spectrum with different frequencies and a guard band. For a TDD-LTE device, this capability eliminates the use of a dedicated diplexer to isolate transmission and receptions, thereby reducing Bill-Of-Materials (BOM) costs.
At C-band, downlink coverage is greater than uplink coverage. This is due to the much larger transmit power of the gNodeB compared to the uplink transmit power of the User Equipment (UE), as well as differences in uplink and downlink time-slot allocations. The application of beamforming technology reduces downlink interference and further increases the gap between C-band uplink and downlink coverage.
Simulations have shown that 5G radio base stations operating at 3.5 GHz combined with advanced antenna techniques such as Multiple-In-Multiple-Out (MIMO) and beamforming can provide the same downlink coverage currently available with LTE 1800 MHz. This allows the existing cell grid to be reused for the initial sub-6 GHz 5G rollout. However, larger MIMO and beamforming arrays are not practical within the limited real estate of a handset. Therefore, if the uplink used the same frequencies as the downlink, the size of the cell would shrink to the maximum range in the uplink, limited by UE power and antenna gain.
Taking the downlink 50Mbps and the uplink 5Mbps as an example, the C-band uplink and downlink coverage differs by 16.2dB. While the C-band downlink can achieve similar coverage as the LTE 1800 MHz, there is limitation in the uplink coverage which becomes a 5G deployment bottleneck negatively affecting the user experience. The difference between C-Band and LTE 1800 MHz uplink coverage is 7.6dB for 2R and 10.4dB for 4R.
Third Generation Partnership Project (3GPP) Release 15 introduced New Radio (NR) Carrier Aggregation (CA) and Supplementary Uplink (SUL) to handle the limited uplink coverage on the higher bands. These mechanisms rely on idle sub-3 GHz band resources to improve C-band uplink coverage and enable 5G services to a wider area. These solutions drive the performance requirements of both base station and mobile device Power Amplifier (PA), RF front-end, and antenna technologies. Depending on the equipment being developed, designers must determine the individual component specifications based on the link budget. The electrical requirements, along with costs and size considerations, play a role in guiding the choice of semiconductor/ integration technology best suited for the target application.
Link budgets are used to predict the received power in a communication system, which is ultimately limited by the achievable Signal-To-Noise ratio (SNR) at the receiver. The received power, in turn, is governed by channel losses and the transmitter’s Effective Radiated Isotropic Power (EIRP), which is equal to the transmit power multiplied by antenna gain. Figure 2 shows the relationship between EIRP, number of antenna elements, available amplifier power at 1dB compression, and dominant semiconductor technologies. Gallium Nitride (GaN) and Gallium Arsenide (GaAs) are the preferred semiconductors in front ends with arrays <100 elements and P1dB >20dBm, which is why III-V technologies are widely used in UE.
For amplifiers designed as either discrete GaAs/GaN transistors on a PCB or as an integrated Monolithic Microwave Integrated Circuit (MMIC), AWR® software offers system, circuit, and electromagnetic (EM) co-design, supporting all phases of PA development. The platform supports concurrent schematic and layout design entry and management, while the AWR APLAC® Harmonic Balance (HB) engine in AWR Microwave Office® circuit design software offers rigorous frequency domain simulation of nonlinear RF networks.
Amplifier designs start with selection of an appropriate active device for the targeted frequency and performance requirements, followed by the development of the bias and impedance-matching circuitry. Biasing and load/source terminations have a strong influence over amplifier performance, hence design aids in AWR software such as DC IV curve generation, load-pull analysis, and impedance-matching network synthesis play a critical role in accelerating early design activity.
The APLAC HB solver verifies amplifier performance with specialized measurements such as Noise Figure (NF) and Small-signal transmission and reflection Parameters (S-parameters), as well as the nonlinear power, gain compression, and efficiency response to large-signal stimuli. In addition, the APLAC HB simulator supports circuit envelope analysis for circuits sourced with digitally modulated signals, providing simulation of key linearity metrics such as Adjacent-Channel power-ratio (ACPR) and EVM.
The 5G NR library option in AWR Visual System Simulator™ (VSS) system simulation software offers easy-to-configure signal sources and receivers that can be used to evaluate RF components and/or RF links using system-level measurements (Figure 3). Testbenches with preconfigured 5G NR TX and RX blocks and measurements support analysis of networks with flexible signal configurations with variable signal power, carrier frequency, Modulation and Coding Scheme (MCS), bandwidth, and subcarrier spacing. These testbenches are used to validate front-end design performance in response to waveforms defined in the 3GPP specifications for sub-6 GHz (FR1), as well as mmWave (FR2) bands.
Because 5G communications is developing rapidly, early delivery of products to market is critical. For engineers at Mitsubishi Electric, the integrated AWR software platform enabled fast development of their 28 GHz GaN PA MMIC, while meeting all technical requirements (Figure 4). Throughout the design process, EM analysis was used for passive component and inter-connect modeling and optimization. AWR AXIEM® 3D planar EM simulator analysis was used to verify the behavior of the Doherty PA’s critical impedance matching/inverting network and output combiner prior to tapeout. In addition, ready access to a design kit for the Mitsubishi Electric GaN process reduced product development time by 50%.
EM analysis and design optimization were carried out at the component and subcircuit level to ensure that parasitics and any inadvertent EM coupling between structures is incorporated into the simulation. Towards the end of the design phase, the Cadence Clarity™ 3D Solver addressed critical interconnect modeling of large-scale, integrated RF/mixed-signal electronic systems. The Cadence industry-leading distributed multiprocessing technology enables the solver to deliver virtually unlimited capacity and 10X speed, which are required to efficiently and effectively address these larger and more complex structures. The Clarity 3D Solver eliminates the need to subdivide structures into smaller sections, which is often necessary to accommodate the capacity limits common among legacy 3D EM simulators.
mmWave Chip, Package, and Board Beamforming Solutions
5G data rates exceeding 1GB/s will be supported by the available bandwidth at mmWave spectrum and use of beam steering phased array antennas and multiple communication chains, which can range from eight to 64 elements in a typical system. A reference design has been developed to demonstrate how software tools from Cadence support the development of such a system from the PCB-embedded 5G antenna array through the package-on-package design and the 45nm Complementary Metal-Oxide Semiconductor (CMOS) receiver RFIC, shown in Figure 5.
The reference design was developed with a full range of Cadence solutions, including:
- AWR VSS software for budget analysis and component specification, phased array configuration, and simulation of digital modulation measurements such as ACPR, EVM, and BER
- Virtuoso® RF Solution and Spectre® RF Option for design entry and simulation of the 45nm CMOS RFIC eight-channel receiver chip
- Cadence EMX® Planar 3D Solver for analysis of on-chip passives and interconnects
- AWR AXIEM simulator for analysis of PCB feed structure and eight-element (4×2) antenna array
- Allegro® PCB Designer for physical layout design
- AWR Microwave Office software for III-V and off-silicon circuit design
System designs often start with budget analysis used to define the RF link, calculate the cascaded performance of the RF link, and determine individual component specifications. The reference design began with back-of-the-envelope approximations taken from published literature, including likely component block performance based on historical results for the target IC process, system requirements (data rates and coverage range), channel losses, allowable transmitter EIRP, and receiver sensitivity. Using VSS, this effort was reduced from multiple weeks down to a few days.
In this case, the thermal noise floor for a 400 MHz bandwidth is calculated to be -85dBm, assuming the receiver has a cascaded NF of 6dB that increases the noise floor to -79dBm, which requires a signal strength of at least -75dBm (per antenna element) to achieve a minimum signal-to-noise ratio (SNR) of 4db. To obtain that received power level (-75dBm), working back towards the transmitter through a Line-Of-Sight (LOS) path loss of 135dB requires an EIRP of 60dBm, which translates into an output power of 33dBm (2w) from the base station PA for an antenna with 27dB of gain.
AWR VSS software was used to characterize the receiver chain with behavioral models, performing budget analysis to obtain the overall cascaded figures of merit and spur heritage to examine the impact of nonlinearities on generating unwanted tones in the system. These analyses helped guide early design decisions such as P1dB and IP3 considerations to reduce unwanted harmonics from device nonlinearities, as well as filtering to mitigate interference. Furthermore, AWR VSS software can perform time-domain analyses from the same schematic to investigate BER, IQ constellation plots, and spectral regrowth, as shown in Figure 6.
After obtaining the desired channel link budget response, attention can be turned to developing the individual RF front-end blocks at the circuit (transistor) level with layout and construction of the eight-channel receiver in both AWR VSS software and the Virtuoso RF Solution. The RFIC was designed in Virtuoso RF Solution using a generic process design kit (PDK) based on 45nm CMOS technology and simulated using the HB engine available in Spectre RF Option. The EMX Planar 3D Solver was used to extract the broadband response of the on-chip passive components and interconnects.
The post-layout Spectre RF Option simulation results were then used to create data files (S-parameter, phase noise mask, spur table, or am/am-am/pm) in AWR VSS software to provide a greater level of detail defining the behavior of the various blocks, thereby increasing the accuracy of the simulation. The schematic, layout, and post-layout simulation results for the individual component blocks are displayed in Table 1.
The next phase of the design focuses on the heterogeneous integration of the RFIC into the packages and development of the PCB with an embedded 2×4 patch antenna array. To implement the packaging, the RFIC design (parasitic-aware schematic) was exported to a SiP as a simple footprint for place and route operations using the schematic-to-SiP layout feature from the RF module pull-down menu in the Virtuoso Schematic Editor. The next step was to bind this footprint to the original IC schematic symbol or sub-circuit using the same symbol that the IC designer has been using in the top-level IC simulations. The Virtuoso System Design Platform provides an intelligent mapping mechanism to create a 1:1 map between the footprint terminals and the IC symbol terminals.
Package-aware RFIC simulation can then be performed based on EM extraction of critical nets from the package design layout. Specific to this design, the Clarity 3D Solver can be used to extract the interconnects between the individual RFIC receiver channels through the package routing to each element of the patch antenna array on the PCB. To focus strictly on the PCB feed and antenna array response, the board layout was imported into the AWR Design Environment platform through the IPC-2581 file format for EM analysis with the AWR AXIEM analysis. In addition to S-parameter extraction, AWR AXIEM analysis can provide surface currents and radiation plots of the individual patch antennas or the entire array (Figure 7).
In addition to EM analysis of the initial array, the designers used the phased-array generator wizard in AWR VSS software to rapidly configure the physical array, assign antenna radiation patterns derived from AWR AXIEM analysis for the individual patch antennas, and model mutual coupling and edge/corner behavior. The wizard also allows designers to specify link and feed performance, incorporate gain tapering to reduce antenna side lobes, and investigate the impact of element failures on the overall array performance. It provides real-time visualization of far-field radiation patterns from all these user-specified parameters and then automatically generates either a system or circuit-based network in AWR Microwave Office software for further development and EM/circuit analysis of the complete array. The resulting array can also be incorporated into the receiver design link.
Conclusion
Next-generation communication systems targeting 5G/6G functionality will provide massive connectivity to the Internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services and business opportunities. The anticipated performance will be made possible through a range of innovative technologies, implemented though complex RF front-end architectures and highly integrated multi-fabric electronics. RF to mmWave design and multi-fabric design and manufacturing software will be critical to the development of these technologies.
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