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How to Achieve a Workflow that Streamlines User Productivity and Capitalizes on Valuable Design/Designer Time

How to Achieve a Workflow that Streamlines User Productivity and Capitalizes on Valuable Design/Designer Time

by Sherry Hess, Product Marketing Group Director, Cadence Design Systems

Early on in my career (aka, during the last century) when I was directing European operations for an EDA firm specializing in electromagnetic (EM) analysis, a customer told me he wasn’t going to buy more software seats because he couldn’t afford to waste valuable “EE” time doing manual drawing to integrate the software’s EM analysis piece of the puzzle into the overall system design. He and his company needed to get the most value from both human capital and software.

Flash forward to today, and this story still resonates. Design-sharing across engineering teams and/or technology domains such RF design, PCB and RFIC/system-in-package (SiP) has been a productivity bottleneck for a long time. The issue is that siloed teams and individual point tools require manual translation and manipulation across IC, packaging, PCB and electronic systems workflows. As we all know by now, this results in late identification of design issues that lead to costly respins and lengthy time-to-market cycles.

With Industry 4.0 and Moore’s Law, devices and applications are only growing more and more complex. As such, chip, package and board designs must seamlessly integrate into full and complete systems in order to provide high-performance electronics at a reasonable cost—all within an ever-shorter market opportunity window.

To win in today’s competitive technology markets, customers require solutions that enable complete design through manufacturing. This, in turn, requires a convergence of engineering teams, design platforms, and simulation and analysis technologies in order to ensure electronic design engineers are spending their valuable time designing and not unnecessarily transferring and translating data from one tool to another. EDA software developers must therefore provide a front-to-back-end interoperable workflow that is as efficient as possible to maximize user productivity.

Change Is Good!

Reflecting back again to when I started my career in EDA, the norm was to use internally developed and supported software solutions. The first evolution of EDA in the systems and analysis space was to move away from the intensive resource drain of home-grown software and to adopt commercially viable, off-the-shelf solutions that enabled designers to start being productive immediately.

We are now in the midst of another wave of EDA change. This time the change centers on having the ability to seamlessly integrate systems and analysis technologies into design platforms and to maximize user productivity. Cadence’s president, Anirudh Devgan, says it best: “Looking back at the last 5 to 10 years, Moore’s Law is driven more by integration than transistor scaling.”

Driving Productivity for Designers

To illustrate this point, let’s look at an IC and its package from decades ago versus where we are today with 3D-ICs that have multiple chips on a package. This is essentially a “system” as these designs require extensive analysis that includes complex cross-fabric component signal integrity (SI) and power integrity (PI) as well as electromagnetic (EM) and thermal. Of course, RF also needs to be considered when these 3D-ICs are supporting 5G and millimeter-wave (mmWave) applications.

As the world grows more complex and competition quickens the pace, we, as software developers, need to make the designer’s job easier instead of harder. Fortunately, Cadence is uniquely positioned to do this. With software IP that spans chip design with the Cadence Virtuoso platform, PCB and packaging design with the Cadence Allegro PCB Designer, and microwave/RF design with the AWR acquisition in 2020, as well as the Cadence Sigrity, Clarity, Celsius, and EMX system analysis technologies, a complete front-to-back-end interoperable workflow is achievable today. Customers are now armed with an integrated chip, package, board design, manufacturing and RF/SI/PI/EM/thermal system signoff platform, empowering design engineers to seamlessly work from the IC out through the complete system. This level of complex, cross-fabric, multi-technology product development streamlines user productivity and capitalizes on valuable design/designer time by cutting out the time wasted and insight opportunities lost when users spend valuable time and cycles to’ing and fro’ing from one tool to another.