RF/Microwave Systems Design Empowered by Cadence AWR Design Environment Version 16

by Cadence

RF-enabled next-generation 5G wireless communication systems and connected devices are differentiated by their performance, size, and cost. Traditionally, custom/proprietary IC designs leveraging the latest advanced-node technology were developed to meet these product requirements, but increasingly these challenges are being met by moving beyond single IC solutions. Today’s electronic systems integrate heterogeneous technologies to mitigate the high cost of homogeneous system-on-chip (SoC) solutions by enabling designers to combine proven RFIC and monolithic microwave IC (MMIC) designs on substrates using newer packaging and integration technologies (Figure 1).

To win today in the highly competitive 5G/wireless markets, customers are demanding solutions that enable complete and comprehensive RF workflows that don’t just start and stop at the chip but extend to the entire system. To this point, engineering teams and electronic design automation (EDA) platforms, as well as simulation and analysis technologies, have converged to ensure that valuable electronic engineering time is spent designing and not unnecessarily transferring and translating data from one tool to another. EDA software developers must therefore provide a front-to-back-end interoperable workflow that is as efficient as possible to maximize user productivity.

Engineers bringing these products to market need best-in-class simulation technology and design automation to accurately predict the performance of larger, densely-integrated circuits/subsystems designed for the broadband and millimeter-wave (mmWave) spectrum. Because these products are developed by diverse engineering teams across multiple design tools, RF design software must also provide interoperability with the broader class of EDA used in the development of mixed-signal electronic systems.

Cross-Platform Interoperability

The latest V16 release of the Cadence® AWR Design Environment® platform redefines what complete and comprehensive RF workflows entail. The V16 software introduces groundbreaking cross-platform interoperability to support RF intellectual property (IP) integration for heterogeneous technology development across the Cadence Virtuoso® design platform, as well as the Allegro® PCB and IC package design platforms, delivering up to a 50% reduction in turnaround time compared to competing workflows. AWR® software, inclusive of Microwave Office® circuit design software, Visual System Simulator™ (VSS) system design software, and AXIEM® 3D planar and Analyst™ 3D finite-element method (FEM) electromagnetic (EM) simulators, also introduces seamless integration with the Clarity™ 3D Solver and the Celsius® Thermal Solver, delivering unconstrained capacity for electrothermal performance analysis of large-scale and complex RF systems (Figure 2).

With the AWR Design Environment V16, Cadence is addressing RF/microwave design and integration through the company’s Intelligent System Design™ strategy, which delivers compu-tational software capabilities across all design elements of electronic systems. At the core of this strategy is design excellence, including an optimized EDA portfolio of tools with best-in-class RF, microwave, and mmWave circuit, system, and EM analysis; IP for semiconductor, package, and PCB design; and scalable access in the cloud.

Platform Interoperability

Leveraging shared architecture/data across Cadence EDA solutions, the AWR V16 release provides new RF workflows that take completed IP design from Microwave Office software and pass both the schematic and layout designs to the Virtuoso and/or Allegro platforms as data in a unified library that contains all the building blocks of the circuit design. This enables design teams to operate the Allegro or Virtuoso SiP bi-directional implementation flow and Virtuoso RF Solution physical implementation flow as the primary layout tool, with AWR V16 software providing the RF IP schematic/layout design data. The Virtuoso RF Solution flow captures Microwave Office RF IP, allowing designers to represent, integrate, and verify the MMIC and embedded-RF package design within a single environment. The shared database enables more practical package and IC co-design by simplifying the design flow with easy and reliable access to RF IP developed within Microwave Office software.

Microwave Office/Virtuoso Workflow

Microwave Office software-generated IP implemented as MMIC or package/laminate technologies can be exported into the Virtuoso Schematic Editor and/or Virtuoso Layout Suite to integrate these designs into multi-technology systems. The new interoperability eliminates the need for manual design re-entry, reducing time, costs, and the potential for errors. Microwave Office software’s sourced schematic and layout designs will have the same look and feel in the Virtuoso environment as the original design. Since most MMIC model and 3D parametric cell (PCell) libraries are defined and implemented by the III-V foundry as a process design kit (PDK), the Microwave Office MMIC design flow continues to utilize this PDK for the target semiconductor process in the design.

Within the Virtuoso RF Solution environment, the Spectre® Simulation Platform engine can simulate the Microwave Office linear models to support IC/module co-design with embedded Microwave Office IP. The ability to import this IP into the Virtuoso flow extends to MMIC designs as well. Since most MMIC model and PCell libraries are defined and implemented by the III-V foundry as a PDK, the Microwave Office MMIC design flow would still utilize this PDK for the target semiconductor process in the design. The resulting MMIC schematic and layout can then be exported as a unified library design for import into the Virtuoso environment, as shown in Figure 3.

Microwave Office/Allegro Workflow

Moving from the chip to the board, an RF-to-PCB workflow starts with the creation of unified libraries and technical files from Allegro parts and board definitions. The new unified library import wizard in the AWR V16 software reads the Allegro symbols and footprints in the universal library and technology file and converts this data into a Microwave Office PDK that can be used to create an RF design using standard design entry and simulation methods. Upon completion of the design, the RF engineer can export the schematic and layout of the subcircuit with all the underlying hierarchy into a unified library design using a new utility in the V16 software (Figure 4).

RF/microwave IP created and analyzed in Microwave Office software can be developed by leveraging Allegro libraries and technologies, ensuring compatibility with the Allegro PCB Designer schematic and layout editors, as well as the targeted manufacturing technologies with corporate-approved components. Using an organization’s approved bill of materials (BOM) eliminates the need to replace components in the RF design when edited inside the manufacturing framework. In addition, physical design constraints set in the Allegro platform are available within Microwave Office software for dynamic voiding of ground/power planes.

The Microwave Office-to-Allegro workflow provides a seamless schematic and layout data transfer from Microwave Office software to the Allegro PCB Design platform, eliminating time-consuming and error-prone manual re-entry. By using parts with identical symbols, footprints, and properties between the Allegro platform and Microwave Office software, RF designs are instantly recognizable to the layout engineer, allowing RF and layout design teams to work collaboratively yet independently. The Allegro design can be imported back into the AWR Design Environment platform for high-performance, multi-physics analysis and design verification of the entire system after the RF IP has been incorporated with the rest of the PCB (Figure 5).

Microwave Office/High-Performance Multiphysics Analysis Workflow

Historically, large RF structures such as phased-array feed networks have been manually sectioned into smaller structures for analysis using the largest and most powerful computing resources. The Clarity 3D Solver 3D EM simulator, used for designing critical interconnect, RFIC/MMIC, module, PCB, and SoIC designs, overcomes the limitations of legacy EM analysis software by leveraging Cadence’s distributed multiprocessing technology to deliver virtually unlimited capacity and 10X speed.

Now integrated within AWR software, the Clarity 3D Solver provides RF designers with ready access to high-capacity EM analysis for design verification and signoff of large, complex RF/ mixed-signal systems beyond the capabilities offered by the AXIEM 3D planar and Analyst 3D FEM solvers.

The Clarity 3D Solver’s integration with the Microwave Office platform is an automated process in which the entire analysis experience is fully within the AWR Design Environment platform. Once the simulation is complete, a dataset with input geometry, simulation setup, and S-parameter results is automatically assembled and associated with the given EM document for plot/measurement and subsequent extraction, circuit simulation, tuning, and optimization. The link also supports mesh, current, and field visualization data in addition to S-parameters, enabling designers to take full advantage of the rich set of EM 3D annotations that already exist in Microwave Office software (Figure 6).

Thermal Solver Integration

IC and electronic system companies, particularly those incorporating IC packaging and/or multi-technology modules, face tremendous thermal challenges that can cause late-stage design modifications and derail project schedules.

The Celsius Thermal Solver embedded within Microwave Office software offers a solution for RF PA and MMIC, RF PCB, and module designs. It supports electrothermal analysis through model information sourced from Microwave Office project information, including existing MMIC (die or packaged device) design data and geometries such as layout, material properties, and power-source values from RF simulation. Celsius Thermal Solver structures can be created either by drawing/importing the geometry in the EM editor or using EM extraction with simulated temperature results automatically returned into Microwave Office software (Figure 7).

3D plots of the thermal temperature distribution can be viewed in the Celsius Thermal Solver’s native editor. For MMIC structures, the solver also provides a full-chip temperature profile at the relevant resolution of the IC layout, available as a graphically viewable 3D structure temperature overlay in the native editor, as well as a temperature-annotated netlist for circuit simulation.

Conclusion

5G wireless systems and connected devices are proliferating across every imaginable industry today, driving technology leaders to capitalize on market opportunities for their RF-enabled products that are defined and differentiated by performance, size, and cost. Designers are adopting heterogeneous technology integration for greater functionality in a smaller footprint, driving the need for design platforms and multi-technology workflows to be interoperable. Cadence’s AWR Design Environment V16 release delivers innovative functionality through seamless cross-platform and multiphysics integration of the AWR platform RF/microwave design IP within the Virtuoso and Allegro design platforms, as well as EM and thermal analysis of complete large-scale designs through the Clarity and Celsius solvers.

Armed with best-in-class RF design, analysis, and EM/thermal system signoff, engineers can now better address cross-fabric, multi-technology product development challenges from the IC through the system level within the comprehensive front-to-back RF workflows offered by Cadence.

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