5G Technology Devices for an O-RAN Wireless Solution – Part 2

by Brad Brannon, Systems Engineer, Analog Devices, Inc.

In Part 1 of this article series (available here), we looked at O-RAN from a system level perspective, including key radio elements, as well as an example signal chain for both the receiver and transmitter. In Part 2, we bring everything together into the full signal chain. We’ll explore various design considerations in more detail, including the clock tree, power dissipation, and tradeoffs that can be made to optimize design for a particular application.

Bringing it All Together

Figure 9 shows the full signal chain including some of the required control signals. For power efficiency, the circuit includes transmit and receive signaling to enable and disable the amplifiers during their respective cycles for TDD. Similarly, this could be used with FDD to power-off during unused slots to save power then as well. An LNA switch is also required to change the input switch on the LNA to shunt any returned transmit power to a termination instead of the core amplifier input. These various signals can be generated and orchestrated by the ASIC, FPGA, or transceiver.

The receiver signal chain includes a function that correspondingly changes the digital data stream to account for the reduced analog gain, preserving the absolute signal level as it is passed to the low-PHY and then on to the remainder of the baseband downstream.

The application shown here is for single band. While the transceiver is broadband and covers all frequencies up to 6 GHz, not all devices in the design do. Devices like the LNA and PA are typically banded and require selection based on band supported. Typically, these devices are available in pin-compatible options to cover all common bands below 6 GHz and are easy to swap out. This enables support for all the popular TDD and FDD bands, including those for 5G and those proposed for O-RAN.

Clock Tree

Depending on the configuration, several different clock configurations are possible. If precise timing alignment is required, then a 2-stage clock synthesis will be required. The first stage will require linkage to the baseband by way of an ASIC, FPGA, or controller to properly time and align the radio digitization. This application will require processing of the precision time protocol (PTP) information provided by way of the fronthaul or by a local GPS receiver. This will ensure that the radio and baseband processor know precisely when radio frames should be processed.

The AD9545 family is ideally suited for precisely adjusting the frequency, phase, and time of the main clock to the radio. It has the benefit that it can be configured to operate temporarily without a reference and maintain accuracy in the case of a faulty or intermittent reference clock when coupled with a TCXO (temperature compensated crystal oscillator) or OCXO (oven controlled crystal oscillator).

For configurations that do not require the precise timing alignment or as the second stage of those that do, a clock distribution device is required. The purpose of the distribution device is to generate the range of clocks throughout the radio. This includes those required for JESD, eCPRI, Ethernet, SFP, and other key signals throughout the radio. The AD9528 provides low jitter clocks to a total of up to 14 different rates, including support for JESD204B/JESD204C device clock and SYSREF signaling.

A 2-stage clock block diagram is shown in Figure 10. For applications that don’t require precise timing alignment, the AD9545 can be eliminated or bypassed and only the AD9528 would be used. The input clock to the system comes from basic network timing and is recovered by the baseband and network functionality of either the Ethernet function block or within the FPGA, depending on the exact architecture. Many alternate configurations are possible, depending on the specific requirements of the radio, with only a representation shown here.

Power

Rolling up the total power dissipation is determined by many factors. Among these factors are the FPGA selected and the functions implemented, the transceiver selected and options enabled, the clock tree required, and the RF power generated.

A typical mid-range FPGA SoC implementing the O-RAN CUS- and M-plane processing, along with synchronization with IEEE 1588 v2 PTP stack, will consume around 15W. The typical ADRV9029 transceiver will dissipate between 5W and 8W, depending on TDD or FDD configuration along with the range of DFE functionality enabled. To this the clocking power, receiver power, and transmitter power, as well as miscellaneous powers, must be added. Table 2 shows an example rollup of the total power for the system exclusive of the transmitter chain, which varies greatly with power output class.

Rolling up the power dissipation for the radio, total dissipation for a 70:30 duty cycle for Tx:Rx shows 26W to 29W, depending on the exact radio configuration excluding power associated with the PA. Table 3 shows a few examples of PA dissipation. Because PAs operate largely in the linear range of the transistors in some variation of a class AB, their efficiency could be anywhere between 20% and 50%. This is where the value of integrated DPD is a big benefit. Even for small bandwidth, low power PAs, a few dozen mW of DPD dissipation is more than offset by the improvement in efficiency of the PA.

For a low power small cell, adding in about 2.5W of additional power brings the total dissipation to about 30W, which is comfortable for a passively cooled indoor small cell powered by a PoE solution.

One potential PoE solution is outlined in Figure 11. This solution includes the LT4321 bridge controller that allows MOS transistors to be used as ideal diodes instead of rectifiers, the advantage of which is much improved efficiency. This is followed by the LT4295, an 802.3bt compliant PD device. This can then be followed by appropriate local regulators to fulfill the requirements shown in the previous table, providing up to 90+ W as required.

Beyond the PoE conversion devices, many other devices are available in support of a small cell reference design. These include cornerstone devices like the ADP5054 family, which is specifically designed to power ADI transceivers as well as many other buck converters and lower noise LDO regulators, as shown in Figure 12.

Options

Such a radio architecture also provides flexibility in terms of meeting a range of market requirements. This architecture is optimized for a range of applications including both FDD and TDD. It is equally capable of performance in low, mid, and high band and is well suited for small cell through massive MIMO platforms. Many different trade-offs can be made in both the transmitter and receiver circuits to optimize for cost, size, weight, and power. While this introduction focused on higher performance and integration, it is possible to make some simple trade-offs in favor of cost with slightly different selections.

For example, some low power PAs do not require a drive amplifier and therefore may not be required. Because the RF power is low for many small cell applications, the circulator may be replaced by a simple TR switch. Finally, if only local area performance is required, the dual stage LNA may be replaced by a simple single stage LNA. The result is a lower cost option still providing good radio performance. An example of this is shown in Figure 13. Many other permutations are available to suit a wide range of possibilities across a wide range of frequency and power options.

The 5G technology devices reviewed here are available for communications applications and enable low cost implementations suitable for 5G development, especially those implementing O-RAN O-RU solutions. These include devices from the RadioVerse family as well as RF amplifiers, clock recovery/synchronization, and power over Ethernet/point of load regulation. Together, this highly integrated set of devices is ready for implementation of 5G small cell, macrocell, microcell, and massive MIMO applications.

When combined with a suitable PHY and software provided in an FPGA, eASIC, or ASIC, a complete O-RU solution may be developed, as shown in Figure 14. This solution was developed with partners at Intel®, Comcores, and Whizz Systems. These solutions meet not only the required RF characteristics but also the cost and power budgets required to enable deployment of low cost, high performance O-RAN platforms.

Sources

1 ftp://ftp.3gpp.org/specs/latest/Rel-15/38_series/

2 O-RAN Alliance.

3 “O-RAN: Towards an Open and Smart RAN.” O-RAN Alliance, October 2018.

4 Brad Brannon. “Where Zero-IF Wins: 50% Smaller PCB Footprint at 1/3 the Cost.” Analog Dialogue, Vol. 50, No. 3, September 2016.

5 Specifications. O-RAN Alliance.

About the Author

Brad Brannon has worked at ADI for 37 years following his graduation from North Carolina State University. At ADI he has held positions in design, test, applications, and system engineering. Currently Brad is developing reference designs for O-RAN and supporting those customers. Brad has authored several articles and application notes on topics that span clocking data converters, designing radios, and testing ADCs. He can be reached at brad.brannon@analog.com.

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