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ART (Advanced Rugged Transistor)


by Tom Dekker, Director Marketing, Multi-Market AMEC, Ampleon

(all figures and tables are at the end of this article)


Ampleon recently released a series of rugged transistors engineered specifically for the industrial, scientific and medical applications which offer robust VSWR ruggedness while delivering the best in terms of RF power, gain and efficiency. We named this series “ART,” short for “Advanced Rugged Transistor.”

ART’s novel Silicon LDMOS node was engineered to obtain a high drain-source breakdown while maintaining a compelling low output capacitance to allow for a rugged transistor with high transconductance in the frequency range from HF through UHF. The ART series has two versions: ART1K6 (50 V VDS / 177 V VDS minimum breakdown) and ART2K0 (65 V VDS / 200 V VDS minimum breakdown range). The high VDS breakdown offers the threshold for VSWR ruggedness features during 65:1 withstand conditions. Further, the low output capacitances allow for frequency ranges of up to 450 MHz with high gain and efficiency. Table 1 provides a comparison of features to our popular BLF188XR (current generation in high volume production) and provides some perspective on comparison to the competitive landscape of devices.

The ART1K6 and ART2K0 are offered in industry standard packages, either air-cavity ceramic or over-mold plastic packages suitable for attaching directly to an amplifier heatsink or copper-coin planar with PCB with gull-winged packages. Class-E designs are enabled at 50 V for ART2K0. Device is within all operating limits of up to 6 dB compression. Testing is underway to extend Class E operation at 50 V to 10 dB compression.

All ART family devices have an internal stability network contained in the die. This network results in close to unconditional small signal stability at low frequency without the need for any external circuitry.

ART Transistor Reference Designs

ART transistors are demonstrated in various reference designs to showcase performance under various application and frequency requirements. Figures 2 through 5 show the existing reference designs, and more are in the works.

 Driver Devices for ART Transistors

To allow for a common voltage rail between driver and output transistor, Ampleon released 65 V ART drivers at 150 W and 35 W (ART150 and ART35). These driver transistors offer the same ruggedized features in an industry standard package to support necessary amplifier topology. Further, Ampleon offers a range of low cost, TO-270 packaged 50 V drivers in our BLP15H series, based on GEN9HV with SWVR of at least 40:1.

ART2K0FE (2kW Si LDMOS Transistor) Applied in a 13 MHz Reference Design (AR#192168)

The 13 MHz amplifier design utilizes a balun transformer combiner with lumped elements deployed with ART2K0FE mounted on a Taconic 30RF35, 30 mm thick, 1 oz. copper cladded printed circuit board material with a heatsink sweat soldered under the PCB. We utilized an even-mode stability network applied to the gate side of the amplifier.

The transfer plots demonstrate gain, power and efficiency under 10%, 20% and 50% duty cycle conditions. The gain plots show an abundance of stable gain at 13 MHz with flat gain expansion over wide POUT levels. Thermal compression is more prevalent under saturated conditions at the 50 % duty cycle versus 20% and 10% as would be expected. The performance achieved at 62 V Vdd is Gp > 28.5 dB, P3dB > 2 kW while achieving > 80% at Psatt.

ART2K0FE (2 kW Si LDMOS Transistor) Applied in a 64 MHz Reference Design (AR#201106)

This 64 MHz amplifier utilizes a coplanar balun fabricated integral in the PCB. This allows for high power combining capabilities in a repeatable PCB fabrication process. This amplifier demonstrates POUT levels > 2180 W at 80% Psat efficiency while delivering power gain of 27 dB.

ART Value Proposition

The value proposition for ART Si LDMOS transistors can be considered in two dimensions: either competitive Si LDMOS or competitive VDMOS. In each case, the ART transistors have compelling advantages.

Comparing to competitive 50 V/65 V Si LDMOS:

  • The highest VDS breakdown on the market, supportive of most rugged VSWR mismatch conditions and offers best margin of safety for 50 ohm and sub-50 ohm mismatch conditions
  • Higher gain, supports low cost, low power driver stages with 2-3 dB more power gain
  • Higher power: 10% more output power

Comparing to competitive 50 V Si VDMOS:

  • Higher output power: 2.5x more output power, which allows for more scalable towards double-digit kilowatt powered HPAs. 2.5 x fewer devices split and combined to achieve necessary power. This is a significant SWaP feature.
  • Higher gain: 7-8 dB more power gain, which allows for lower drive power levels
  • Higher efficiency: significantly more efficient performance by almost a factor of 2x (45% VDMOS vs 80 % LDMOS). This is significant on many levels.
  • System advantages of 50 V Si VDMOS:
  • Power supply DC power levels 2x less with LDMOS
  • Thermal management dissipated power levels 4x less with LDMOS
  • Operational costs for industrial applications which operate 24 hours a day/7 days a week: the operational cost saving of a LDMOS amplifier is half compared to VDMOS. This can approach $10,000 of utility bill savings per amplifier on an annual basis.

Figure 1: ART Si LDMOS transistor products
Figure 2: Wire-wound, Ferrite Core Balun (re-position to ART192168)
Figure 3: 64 MHz Planar Balun (re-position to ART201106)
Figure 4: 13 MHz and 27 MHz Binocular Balun HPA
Figure 5: Driver Devices for ART Transistors
Figure 6: (Swept Duty Cycle) drain efficiency (%) as a function of POUT (dBm)
Figure 7: (Swept Duty Cycle) gain (dB) as a function of POUT (dBm)
Figure 8: 63 V pulsed gain vs POUT (10 μs 20%)
Figure 9: 63 V pulsed gain vs efficiency (10 μs 20%)
Table 1: Comparison of rugged 50 V / 65 V Si LDMOS in comparison to Si VDMOS
Table 2: Single Frequency Reference Designs
Table 3: Multi-Frequency Reference Designs
Table 4: Driver Device Reference Designs 1 @ 10-54 MHz 2 @ VHF
Table 5: Driver device reference designs at 65 V