Low Phase Noise DAC-Based Frequency Synthesis for Fast Hopping Wideband Microwave Applications – Part 2

by Ben Annino, Applications Director, Analog Devices, Inc.

In Part 1 of this article series (available here), which ran in the January issue of Microwave Product Digest, we discussed phase noise implications in EW and radar applications. Next we covered what has changed in terms of implementing high-speed DAC-based synthesis, how wideband microwave synthesizers can be designed using high-speed DACs, and new clocking challenges that arise with this approach. In Part 2 of this article series, we’ll carry these concepts forward and cover a microwave synthesizer implementation in detail.

Figures 1 – 11 and Equations 1 -3 were printed in the January 2022 issue of Microwave Product Digest

(all figures are at the end of this article)

Microwave Synthesizer Implementation

Up to this point, we’ve considered the options in implementing the sample clock source relative to the DAC additive phase noise potential. Now we will consider the tuned generator implementation. The designer chooses a data converter sample clock frequency based upon a multitude of DAC and ADC objectives, including Nyquist zone, instantaneous bandwidth, and data payload, among others. A fun puzzle is how to efficiently frequency plan the generation of a set of fixed tones from the available sample clock and the subharmonic, N-harmonic, and /N brethren thereof. These fixed tones are the coarse frequency set that are mixed with the fine frequency set output from the DAC.

Figure 11 (found in Part 1 of this article) is a block diagram of the coarse/fine mixing scheme. In this example, we are using the MxFE® RF ADCs AD9081/AD9082 with the sample clock at 12 GSPS from a VCO that also outputs RF/2 at 6 GHz. These tones come for “free” because you need them to clock the DAC, so it makes a lot of sense to base the coarse tone generator around them. It works out that 18 GHz feeding a programmable frequency divider to single sideband mixer scheme creates a set of coarse frequencies that, when mixed with the DAC output, allow synthesis coverage across most of Ku- and K-bands. Tunable bandpass filters are critical to attenuate many mixing and DAC spurs. A precision DAC translates the SPI control to a low noise analog control signal tuning the tunable filter (for example, ADV7125).

Of course, this mixing scheme sounds a little complicated, and a brute force simpler option is to frequency multiply the DAC output instead of mix. Frequency multiplying is attractive because it is simpler and has lower SWaP-C, as the orange highlight functional blocks in Figure 11 are replaced with the multiplier functional block in Figure 12b. The problem with frequency multiplying, and why we don’t seriously consider it as an option here, is the 20LogN DAC noise floor and DAC spur degradation. The direct RF DAC output has excellent additive phase noise and spurious (generally miscellaneous spurs generated from DACs are well below 60 dBc). But to translate a 3 GHz to 6 GHz DAC RF output up to Ku-band, a multiply of 4 is needed at a minimum, which is a 12 dB degradation in DAC spurs and phase noise. From a mission standpoint, there’s a good chance this 12 dB degradation takes DAC spurs and noise from compliant to noncompliant.

The added complexity of the coarse/fine mixer approach is worth the trouble because it avoids multiplying the DAC, and thus the DAC spur and phase noise level are translated 1:1 to the upconverted RF output (not increased by 12 dB!)

Figure 13 through Figure 16 illustrate how the coarse and fine SSB phase noise combine to make the final SSB phase noise at the desired upconverted microwave frequency. Measured phase noise numbers are shown later in Figure 18 through Figure 20. Frequency multiplying is the same as mixing a signal with a copy of itself. Likewise, mixing coherent signals of different frequencies has the same 20LogN phase noise impact as multiplying. In other words, in Figure 13 through Figure 16, in the offset regions annotated “coherent,” there is no phase noise benefit from employing the mixing vs. multiplying approach. In upconverting the sample clock shown in gray to a higher LO frequency, the entirety of the phase noise curve is simply translated up 20LogN. The primary motivation for coarse/fine mixing is the benefit achieved at larger offsets as the phase noise shoulder approaches the noise floor. Because the LO coarse tone phase noise plunges far below the DAC additive noise level at these offsets, it contributes essentially nothing, and you just see the DAC phase noise translated 1:1 to the upconverted microwave signal. Figure 16 compares the final synthesizer phase noise for each approach and annotates the far offset benefit from mixing vs. multiplying.

Figure 17 is the component chain used in the lab to get the measured SSB phase noise shown in Figure 18. An ultralow noise 100 MHz crystal oscillator is multiplied by 60. The resulting 6 GHz reference phase noise in Figure 18 has a floor of –137 dBc/Hz. As a sanity check, this puts the 100 MHz crystal noise floor plus additive phase noise of the multiplication chain at –173 dBc, which makes sense. The reference 6 GHz signal feeds the LO port of the HMC558 double balanced mixer, which is used as the analog PD. (Note that the IF port of the mixer must be DC coupled.) The PD constant (K_PD) of the mixer is needed to calculate the op amp active filter values. This is measured experimentally using a mechanical delay line and voltmeter. The experimental setup measured both a DRO and MMIC VCO (HMC1166) at the RF oscillator spot. Because K_VCO is a lot different between the two, different loop filter values are required. HMC606 is used so that the amplifiers do not add residual phase noise.

As mentioned earlier, 6 GHz is chosen as the PD comparison frequency based upon the multiplied reference floor level at –137 dBc/Hz. The in-loop phase noise will be raised 20Log10 (12/6 GHz) = 6 dB, expressed as N=2. At this reference noise floor level, the op amp, frequency divider, and amplifier residual noise in the opposite leg are sufficiently below the reference floor so that they do not contribute. If 3 GHz PD frequency is chosen instead, the reference floor goes to –143 dBc/Hz (6 dB improved vs. 6 GHz scenario) and N=4 (6 dB worse vs. 6 GHz scenario), so the reference absolute phase noise impact to the final phase noise is a wash as the frequency scales up or down. However, the additive noise of the in-loop divider, amplifier, and op amp must now effectively be 6 dB better to remain non-contributors at 3 GHz. As the PD frequency lowers, you’ll reach a point where this additive noise dominates. Going the other way and increasing the PD frequency to 12 GHz removes the additive noise of the in-loop frequency divider (good) and might be viable. The additive noise of the RF amplifier will increase with frequency, but might be fine at 12 GHz. K_PD would need to be remeasured at 12 GHz. The 12 GHz PD setup was not evaluated for this article, but this setup may work just fine.

 If implemented in a product, a lock acquisition circuit is needed. This was not demonstrated. V_TUNE needs to be “precharged” to steer the VCO frequency close enough to the reference so that lock can be captured.

In Figure 19, the measured phase noise results were impressive using the HMC1166 with analog PLL and AD829 op amp active loop filter. Using the same HMC1166 VCO, we demonstrated ~15 dB improvement using the analog PLL vs. the HMC440-based implementation using 1 GHz at the PD. Most importantly, the offset over which the clock dominates the phase noise is limited to 200 kHz to 2 MHz, and the worst-case degradation from the DAC additive phase noise is ~10 dB. Contrast this with the HMC440 implementation where the clock dominates an additional decade from 20 kHz to 2 MHz with a worst-case degradation of 17 dB from the DAC additive noise. At close offsets, the VCO APLL tracks the reference phase noise, with a bit of peaking from the loop filter at mid-offsets. This region around 500 kHz might be improved with further iteration. A suggested technique that showed promising results in modeling is to cut down the KVCO of the VCO. The above scenario uses readily available COTS components and is reasonably easy to demonstrate at low cost.

The really exciting performance came from the DRO scenario in Figure 20, albeit at higher SWaP-C. Reflecting on the DRO APLL performance, we nearly got it low enough to be invisible under the DAC phase noise. The DAC RF output phase noise does bump up a few dB in the 10 kHz region where the CLK peaks close to the DAC phase noise. The loop bandwidth is quite narrow in order to get the optimal transition point to the very low DRO phase noise. The peaking of the DRO APLL is suspected to be op amp noise. Overall, we feel the objective was met within a couple dB and can recommend a 12 GHz DRO locked using an analog PLL for the lowest phase noise synthesizers needing the full phase noise capability from MxFE devices.

 Other Benefits of Using a DAC-Based Mixer Synthesizer

In addition to phase noise benefits, the MxFE DAC-based coarse/fine mixer synthesizer is capable of ~300 ns agile frequency hopping when in fast frequency hop (FFH) NCO-only mode. When hopping among the 32 independent NCOs, frequency hop phase coherency is maintained, as shown in Figure 21. Additionally, this synthesizer is not limited to just agile tone generation. The DAC provides the flexibility to implement arbitrary modulation implemented via the JESD204B/ JESD204C datalink.

Conclusion

The excellent phase noise exhibited in ADI’s latest generation of high speed DACs (AD9162, AD9164, AD9172, AD9174, AD9081, and AD9082, for example) enables SWaP-C benefits in next-generation low phase noise, fast hopping, agile RF/microwave synthesizers. The fixed DAC sample clock must have very low SSB phase noise that is beyond the capability of mainstream wideband VCO-PLLs. Analog PDs can offer 10 dB to 20 dB of in-loop phase noise performance improvement vs. conventional active PFD-based PLL synthesizers. To meet the most demanding phase noise system requirements, the suggested fixed clock implementation is a DRO locked using an analog PLL. DAC-based coarse/fine mixer synthesizer examples, measured phase noise results, and an application circuit are provided.

References

Acar, Erkan. “The Path to Lowest Phase Noise: A Fully Integrated Translation Loop.” Microwave Journal.

Annino, Benjamin. “SFDR Considerations in Multi-Octave Wideband Digital Receivers.” Analog Dialogue, Vol. 55, No. 1, January 2021.

Collins, Ian. “Phase-Locked Loop (PLL) Fundamentals.” Analog Dialogue, Vol. 52, No. 3, July 2018.

Collins, Ian and Mailloux, David. “Revolution and Evolution in Frequency Synthesis: How PLL/VCO Technology Has Increased Performance, Decreased Size, and Simplified Design Cycle.” Analog Devices, Inc., January 2020.

Delos, Peter and Liner, Jarrett. “Improved DAC Phase Noise Measurements Enable Ultralow Phase Noise DDS Applications.” Analog Dialogue, Vol. 51, No. 3, August 2017.

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