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Designing Microwave PCBs Right the First Time

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by John Priday and John Leafe, Teledyne Labtech

With improvements in processor speed and model accuracy, it is more and more common for microwave circuit simulations to bear a close approximation of their eventual performance. However, not all pitfalls present in successfully manufacturing a complex microwave circuit are captured in simulations. This article examines common mistakes, how to adjust your design to avoid them, and other useful points.

Figure 1 shows some common issues in stylized and exaggerated form in the following sections:

Figure 1: Some common issues on a microwave PCB

Misalignment through choice of material with insufficient dimensional stability for the application

  • Pad lift
  • Peeling traces
  • Thermoplastic movement of features
  • Extreme bowing because of coefficient of thermal expansion mismatch between materials
  • Impossible to produce blind vias
  • Accidental stub antennas
  • Printed embedded resistors with too little area to maintain value accuracy
  • Poor solder joint due to gold embrittlement

Modern PCBs are made from material-pressed and bonded layers. Typical layers (“base laminates”) start completely covered top and bottom with copper (“copper foils”), most selectively removed during processing steps, leaving only the desired traces, ground planes, etc. Plated-through holes (PTH) are constructed to connect traces on different layers together, and commonly used components such as resistors can be embedded inside the layer stack or created from the selective laying down of resistive material.

Typically, the top and bottom layers will have most of the desired electrical components mounted on them, with connections between component and trace achieved with soldering or wire bonding. The composition of the underlying layers significantly affects microwave performance and the expected environment’s physical behavior.

With this in mind, let’s examine the different stages as shown in Figure 2:

Figure 2: Order of discussion
  1. Base laminate material, which greatly affects performance at frequency through factors such as dielectric coefficient (Dk) and loss tangent (Df)
  2. Choice of copper foils supplied with the base laminate
  3. Bond films that glue the stack together
  4. Buildup of the multi-layer stack
  5. Via types and spans
  6. Embedded resistors
  7. Surface finish

One question frequently asked is the primary cost drivers and what can be done to reduce the cost. This is always challenging because there are invariably good reasons for the multiple via stacks or tight tolerances specified, but we will look at some trade-offs.

Base Laminates

The choice of base laminate materials is one of the earliest design decisions, affecting performance and cost. There are many different materials available. From a designer’s point of view, Dk and Df will be paramount. The type of copper foil will also factor into the losses within the circuit, with low-profile coppers often being selected where losses need to be minimized. Below is a list of considerations:

  • Dimensional stability
  • Metal backed (pre-bonded) – a type of backing: copper, brass or aluminum
  • Coefficient of  Thermal Expansion (CTE) is especially important for multilayer circuits
  • Glass Transition Temperature (Tg) or melt point for thermoplastics
  • Type and percentage of filler within the substrate

Dimensional stability can be a major issue, especially for larger circuits, and although dimensional changes during processing (usually shrinkage) can be allowed for by scaling, consistency is key to successful production with high yields. Generally, materials with some reinforcement (e.g., woven glass) give more consistent results. So where can this hurt you?

Scaling does not solve the issue of material with poor and unpredictable dimensional stability, as the dimensional change varies from piece to piece. It is common to make very large phased array antennas up to 1.2 x 1.2 m in which alignment relies on accurate distances from physical mounting holes. If radiating elements on the board match precise apertures in a machined metal piece, as shown in Figure 3, the placement of the elements wanders off relative to the metal (from correct placement at (i) to significantly offset in (ii)), loss and efficiency of the antennas will suffer.

Figure 3: Accumulating positional errors due to poor dimensional stability of the laminate material

A different issue is when designers use dimensionally-stable materials, but specify extremely tight tolerances, believing this will insulate them from issues resulting from process tolerances. While this may be necessary in some designs, it increases cost and scrap. Expanding tolerances in modeling tools often shows that some design aspects are less sensitive than might be assumed, and relaxation will significantly aid manufacturability.

Metal-backed circuits can present challenges in terms of overall thickness for processing. The applications are usually for high-power RF, so backings greater than 6 mm are common. The maximum total thickness for Teledyne’s standard processes is 8 mm, and aluminum can be plated through holes, blind vias and the final finishing of exposed aluminum.

The CTE of a material is an essential consideration for both the end use and throughout the manufacture of the PCBs. Mismatches can lead to stresses within the structure that can result in bowing; they can also lead to stresses in solder joints where the CTE of components is significantly different from the overall CTE of the PCB, sowing the seeds for poor reliability later. It is safest to use the same materials throughout the stack whenever possible. Designs will often combine microwave circuits with digital logic control circuits using FR4 for the latter to save cost; this sets up likely CTE issues unless designs are symmetrical with the distribution of CTEs balanced across the board.

Another consideration is the Tg. For FR4, this is typically between 120° and 140° C. Tg is typically greater than 170° C for high-quality microwave materials, and most high-reliability applications call for high Tg materials. This is important as CTE generally makes a step change when the Tg is exceeded, sometimes changing by a factor of three or four.

As lead-free soldering calls for temperatures of 230° C, increased CTE above Tg can mean increased stresses on features such as PTH vias, pads etc., particularly in the Z direction, leading to pad-lift after cooling. This is shown in Figure 4 (i) from the sketch in Figure 1 (ii), and magnified in (iii) shows a cross-sectional photo of a real example of pad-lift.

Figure 4: Example of pad lift that can occur after thermal stress (288° C solder float for 10 s). Note in (ii) that the via hole is filled with solder due to the solder float test. Pad lift/land lift (magnified in (iii)) occurs because the Z axis CTE of the substrate is much higher than the copper of the hole wall, and the PCB goes through an elevated temperature cycle if the Tg of the substrate is exceeded.

Materials with higher Dks usually have high filler contents that can be very abrasive to drills and cutters. In these cases, processing costs will be increased because more drills and cutters are required for each circuit.

Copper Foils

Laminate layers are available with a variety of copper foils. The most common is electrodeposited. The type of copper foil used will impact the RF performance, especially at higher frequencies. Typically the types of copper foil available and associated backside surface roughness are:

  • Electro Deposited (ED) – 1.5 μm RMS but can be as high as 3.0 μm RMS
  • Reverse Treated (RT) – 0.7 μm RMS
  • Rolled Annealed (RA) – 0.3 μm RMS

The impact of these choices is shown below for an operating frequency of 25 GHz using the same substrate.

  • 0.02 in. RO3003 with 0.5 oz. RA copper versus 0.5 oz. ED copper: ED loss is about 0.1dB/in. higher.
  • For 0.005 in. RO3003 with 0.5 oz. RA copper versus 0.5 oz. ED copper: ED loss is about 0.35 dB/in. higher.

Increased surface roughness will increase transmission losses (dB/mm). The losses will increase with frequency and reduced substrate thickness, which becomes important for long trace runs on large substrates. However, this is a trade-off in two ways. Smoother surfaces take more steps to process and are more costly as it is more difficult to bond subsequent layers, and copper’s peel strength will be lower, making scrap more likely and rework difficult or impossible. Some materials, like the Rogers 4000, are unavailable with RA copper.

Figure 5: Peeling of traces is more likely after rework if the back side of the copper was smoother initially—the trade-off between lower loss, and lower adhesion
Figure 6: PTH via having moved relative to top-level artwork because of the flow of thermoplastic material in a later stage at too high a temperature

Bond Films

With so many prepregs and bond films available, there is much to consider. The following criteria must be considered to assist in selecting different categories of bond films as well as ensure the electrical properties are appropriate:

  1. Thermoset or thermoplastic?
  2. Bonding temperature. Will all the materials within the build withstand the bonding temperature? (e.g. base laminates, plugging paste, embedded components, solder, silver epoxy, etc.)
  3. Will the bond film withstand subsequent assembly stages? SMT assembly or hand assembly?
  4. Are there multiple bond stages? If there are, thermoset bond films/prepregs make life easier but aren’t essential. Thermoplastics can still be an option if bond films are used with different melt points and the bond film with the lowest melt point is used last.
  5. Are there filled vias? Within a sequential build, there is often the requirement to fill buried via holes. Depending on the number and size of vias and the prepreg used, one option is to fill these with resin flow from the prepreg during bonding. However, if the volume is too much, holes must be filled using a high-solids-content plug paste.
  6. If there are internal cutouts where resin flow needs to be controlled, no-flow or low-flow prepregs must be used.

Thermoset materials don’t re-melt, while thermoplastics will soften, so circuits composed of thermoplastic materials will tend to move or come apart if you go above a set temperature. This is fine if you sequential bond, but start with the highest temperature thermoplastic materials first, then work down to those with lower temperatures in subsequent steps so the earlier ones do not re-melt.

For example, if a board has PTH vias running through it and is heated so that thermoplastic films soften, they could “swim” and melt in subsequent bonding steps. Unless everything is perfectly flat, features could wander off.

Multilayer Build-Up

Applying simple basic rules can help aid manufacturing and can be applied from the outset. We recommend applying these three rules to help maintain flatness when considering the initial build-up.

a. Minimum risk is achieved when the same material and bond film are used throughout

b. When different materials must be used, keep the build-up of laminates and bond films symmetrical

c. When neither of these options is possible, use a 1: >2.5 rule if an asymmetric design is required so there is a significant difference between materials. This will help minimize the effects of mismatched CTEs between the materials by making one material dominant.

When a circuit is constructed as sub-boards, i.e., multiple bonding stages, it is important that the scaling of the sub-boards match, as the asymmetry within a sub-board stack can cause issues in manufacturing. For example, if sub-boards are significantly bowed due to a CTE mismatch of materials, it can be extremely difficult to process even if the final build is symmetrical once all the parts are together.

Figure 7: Illustration of layer bowing
Figure 8. Example of extreme bowing

An example of extreme bowing is shown in Figure 8. Here board layers were removed from a press on a leaderboard. As shown in the left photo, the two bowed layers roll up like scrolls upon pressure release. Subsequent unrolling shows evidence of distortions arising from CTE mismatch stresses.

Via Types and Spans

Traditionally connections are made via plated through-holes running through the complete stack. As complexity has increased, it has become necessary to have multiple different via spans, with an example shown in Figure 9 (i). Figure 9 (ii) shows via spans and four bond stages (B1 to B4). The order and sequence must be considered carefully.

a. L1 to L4 is drilled through sub-board with plated and filled vias (B3)

b. L12 to L13 laser-drilled blind holes may be copper-filled (B1).

c. L11 to L15 drilled through sub-board with plated and filled vias (B2)

d. L1 to L10 drilled through the entire stack, plated and back drilled from L15 (B4)

e. L1 to L12 drilled through the entire stack, plated and back drilled from L15 (B4)

 f. L1 to L15 drilled (B4)

Figure 9. (i) A board with complex via spans. (ii) A hypothetical stack build-up

Sub-boards allow through-drilling before complete assembly, minimizing the need for blind vias. The aspect ratio of hole length to diameter must be considered in each case. Holes drilled as blind should have a maximum aspect ratio of 1:1 and through holes not greater than 12:1. Particularly with small geometries, the aspect ratio can be a big issue, as the plating process involves getting a solution into a small hole, getting air out of it, and getting solution movement within it, with physics and chemistry working against achieving an even and unbroken coating.

Figure 10: Insufficient back-drilling depth leaving a stub antenna

While through holes are most desirable, sometimes, in complex structures, blind vias cannot be avoided. These can be constructed as through-hole vias and then back-drilled. Back-drilling accuracy is essential, as drilling too deeply will cut through the pad, severing the intended electrical connection; drilling too shallow leaves the connections safely intact, but also excess conductor which can act as a stub antenna, radiating unintended microwave energy (Figure 10).

Where holes are back drilled, the stub that remains before reaching the target layer will nominally be 100 μm long +/-25 μm. We recommend that holes to be back drilled are prefilled with a high solids content paste and cured before back drilling. This is especially important if PTFE-based substrates are being used.

In some cases, blind vias between particular layers or locations may not be possible. In Figure 11 (i), the placement of logic lines on the top layer denies access for back-drilling to layers below. The case shown in (ii) has layer connections that cannot be built up through vias from two sub-boards, as the spans overlap.

Embedded Resistors

It is increasingly common to embed discrete components such as resistors inside boards. A typical application is the formation of a Wilkinson divider in a phased array system, where two separate layers will often support a divider network each. Embedding reduces the overall size of the assembly. Traditionally, discrete chip resistors were used, and this still makes sense if the power dissipation of each resistor is greater than 200 mW or the value tolerance must be within tight limits. Otherwise, it is more cost-effective to use printed resistors, which are deposited as part of a layer and are particularly beneficial where tens or hundreds of components are required. Teledyne Labtech offers the following options:

a. Discrete chip resistors soldered in place

b. Discrete chip resistors attached using conductive (Ag epoxy) adhesive

c. Ohmega-Ply® or Ticer® foil printed resistors

d. Discrete resistors using Ohmega-Ply or Ticer foil

When discrete embedded chip resistors are to be fitted using solder, the liquidus temperature of the solder must be greater than 40° C higher than the bonding temperature of the bond film/prepreg. Discrete chip resistors are usually only required when tighter than +/-10% tolerance of resistance values is required, and power dissipation is more than 200 mW, although this depends upon the area of the resistor element. For 50-ohm-per-square Ohmega-Ply, the power versus resistor patch area (with A in mm2 ) is (mW = 173 x A 0.35). There is a trend toward using printed resistors using Ohmega-Ply or Ticer foil where tolerances of +/-10% can typically be achieved when using 50-ohm/square material.

Figure 11: A case where blind vias are impossible as sequential build-through vias. Either (i) or (ii) will have to be processed as blind vias with an aspect ratio of 1:1 or less
Figure 12: Discrete embedded chip resistor (left) and printed resistor with too little surface area (right)

Financially there is a clear benefit to using printed resistors when there are many resistor elements per circuit. However, it is important to avoid minimal geometries, i.e., not less than 0.2 x 0.2 mm for 50 ohm/square, so manufacturing tolerances do not significantly impact the final resistor values. To minimize RF losses, it is preferred to utilize Ohmega-Ply or Ticer foil as “discrete” resistors that avoid the presence of the resistive layer under the conductors carrying the RF signals. An example of an embedded chip resistor is shown in Figure 13 (i), and a printed embedded resistor formed using Ohmega-Ply is shown in (ii).

Figure 13: Embedded chip resistor (i) and printed resistor (ii)

Surface Finishes

The surface finish of the conductors is important on an RF circuit and can directly impact the performance. This does depend on what signal traces are on the outer surfaces of the PCBs. Stripline designs may only have small surface interface pads, so an industry-standard electroless nickel immersion gold (ENiG) finish is acceptable. However, when signal traces are on the surface, ENiG is generally considered too lossy, especially if the path lengths are extended beyond a few millimeters.

Most available plated finishes are less conductive than copper, increasing the conductor losses. Immersion silver, however, does not have any detrimental impact on performance, although it is very sensitive to handling and cannot be readily reworked. The losses due to ENiG rise with increasing frequency and with the reduction in substrate thickness. Solder masks should not be applied over RF signal traces as this will increase losses and, where necessary, be limited to small dams to control solder flow.

Figure 14: A solder joint on a layer of gold that is too thick can lead to solder embrittlement

Electroless nickel palladium immersion gold (ENEPiG) is slightly less lossy than ENiG and is favored for Ka-band and higher frequencies, especially where both SMT assembly and gold wire bonding are required. In all three cases, ENiG, immersion silver and ENEPiG are electroless/immersion (ion exchange) processes that coat all surfaces of exposed conductors, including track edges, so they are relatively straightforward to apply and provide a uniform thickness. Immersion silver is the lowest cost, and ENEPiG is the highest, driven by the palladium content.

Pure soft gold 3 to 5 μm thick is often required when wire bonding over a nickel layer of 1 to 3 μm. If soldering is also required, the gold is plated selectively with wire bonding sites being 3 to 5 μm and the remaining traces being kept below 1 μm to avoid gold embrittlement issues with solder joints.

This type of finish must be applied before etching the track features as it is a galvanic process and requires all features to be connected, so the edges of the tracks will have exposed copper on the finished circuits. Figure 15 shows a typical cross-section of gold over nickel over copper of a track on a high Dk substrate. This finish is more expensive than the electroless/immersion processes.

Figure 15: Typical cross-section of gold over nickel over copper of a track on a high Dk substrate. The substrate is typical of high-Dk materials where the base material, such as PTFE, has particles of materials such as alumina trapped within it to raise the overall dielectric coefficient.

When contact pads are required for edge connectors or spring-loaded contacts, hard gold can be selectively plated with a nickel underlayer to provide a more durable surface.

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